diff --git a/src/coreclr/jit/scopeinfo.cpp b/src/coreclr/jit/scopeinfo.cpp
index 5c9c4077ec4ea1..2278f18655567a 100644
--- a/src/coreclr/jit/scopeinfo.cpp
+++ b/src/coreclr/jit/scopeinfo.cpp
@@ -942,7 +942,7 @@ void CodeGen::psiBegProlog()
             if (!isStructHandled)
             {
 #ifdef DEBUG
-#ifdef TARGET_LOONGARCH64
+#if defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
                 var_types regType;
                 if (varTypeIsStruct(lclVarDsc))
                 {
@@ -961,11 +961,15 @@ void CodeGen::psiBegProlog()
                 else
                 {
                     regType = compiler->mangleVarArgsType(lclVarDsc->TypeGet());
+#ifdef TARGET_LOONGARCH
                     if (emitter::isGeneralRegisterOrR0(lclVarDsc->GetArgReg()) && isFloatRegType(regType))
                     {
                         // For LoongArch64's ABI, the float args may be passed by integer register.
                         regType = TYP_LONG;
                     }
+#else // TARGET_RISCV64
+// For RV64GC -mabi=lp64d is assumed, so floats are not passed through integer registers.
+#endif
                 }
 #else
                 var_types regType = compiler->mangleVarArgsType(lclVarDsc->TypeGet());
@@ -973,7 +977,7 @@ void CodeGen::psiBegProlog()
                 {
                     regType = lclVarDsc->GetHfaType();
                 }
-#endif
+#endif // defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
                 assert(genMapRegNumToRegArgNum(lclVarDsc->GetArgReg(), regType) != (unsigned)-1);
 #endif // DEBUG
                 varLocation.storeVariableInRegisters(lclVarDsc->GetArgReg(), REG_NA);