Skip to content
View Carlos-Jr's full-sized avatar
🤖
Programando...
🤖
Programando...
  • Brazil

Block or report Carlos-Jr

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Carlos-Jr/README.md

Hello there!

I’m an Industrial Automation Engineer with a strong foundation in computational modeling and a deep focus on energy-efficient digital design. My Ph.D. research targets the optimization of digital circuits at the gate level, aiming to approach the thermodynamic minimum of energy dissipation as defined by Landauer’s limit.

🔧 Automation Engineer | 🎓 M.Sc. in Mathematical and Computational Modeling | 📘 Ph.D. Candidate in Engineering 🧠 Research in Digital Circuit Optimization at the Logic Gate Level, grounded in Landauer’s Principle

But it’s not all bits and boolean! I also explore: 🤖 Robotics – because making machines move is magic. 📟 Embedded Systems – where hardware and software meet. 🔌 Electronics – the foundation of it all.

Pinned Loading

  1. neumatic-mod neumatic-mod Public

    Forked from picuino/neumatic

    Mod of the Neumatic Picuino Pneumatic Simulator

    HTML

  2. circuitropy circuitropy Public

    A library for inspecting combinational digital circuits from Verilog netlists, focusing on exploring energy limits based on Landauer's principle.

    Rust

  3. prog.me prog.me Public

    Repositório para projeto de extensão no IFMG campus Ibirité, de ensino de robótica e programação

    CSS

  4. verilog-benchmarks verilog-benchmarks Public

    Coleção organizada de netlists Verilog combinacionais (EDGE, EPFL, adders BCGEN) para benchmarks

    Verilog