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nvme support for iPad 7 #3

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5d758f1
apple: t8010: add clean H9P NVMe storage
Pauli1Go Jun 28, 2026
60287da
apple: t8010: use upstream DART for H9P NVMe
Pauli1Go Jun 28, 2026
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237 changes: 237 additions & 0 deletions Documentation/devicetree/bindings/pci/apple,t8010-pcie.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/apple,t8010-pcie.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Apple H9P/T8010 PCIe Host Controller

maintainers:
- Hector Martin <marcan@marcan.st>

description:
Apple A10/T8010 devices use an older H9P PCIe root complex for the
internal storage path. It exposes one ECAM window shared by up to four
root ports, controller-specific PHY and port register windows, and a
controller-local MSI block.

allOf:
- $ref: /schemas/pci/pci-host-bridge.yaml#
- $ref: /schemas/interrupt-controller/msi-controller.yaml#

properties:
compatible:
const: apple,t8010-pcie

reg:
minItems: 10
maxItems: 10

reg-names:
items:
- const: config
- const: phy0
- const: phy1
- const: phy2
- const: port0
- const: port1
- const: port2
- const: port3
- const: nvmmu0
- const: pcieclk-postup

interrupts:
description:
Four port state interrupts followed by 32 MSI interrupts and the
optional NVMMU fault interrupt for the active storage port.
minItems: 37
maxItems: 37

clocks:
minItems: 3
maxItems: 3

clock-names:
items:
- const: core
- const: aux
- const: ref

power-domains:
minItems: 3
maxItems: 3

power-domain-names:
items:
- const: core
- const: aux
- const: ref

reset-gpios:
description:
PERST# GPIOs indexed by PCIe root port.
minItems: 1
maxItems: 4

clkreq-gpios:
description:
CLKREQ# GPIOs indexed by PCIe root port.
minItems: 1
maxItems: 4

msi-controller: true

msi-parent: true

apple,msi-doorbell:
$ref: /schemas/types.yaml#/definitions/uint32
description:
MSI doorbell address programmed into downstream endpoints.

apple,enabled-ports:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Bitmask of root ports that should be powered and trained.
minimum: 1
maximum: 15

apple,nvmmu-iova:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Base device-visible address for the reserved NVMMU/SART window.

memory-region:
description:
Reserved physical window programmed into the H9P NVMMU/SART path.
maxItems: 1

interrupt-controller: true

'#interrupt-cells':
const: 1

required:
- compatible
- reg
- reg-names
- interrupts
- clocks
- clock-names
- power-domains
- power-domain-names
- reset-gpios
- clkreq-gpios
- bus-range
- ranges
- msi-controller
- msi-parent
- apple,enabled-ports
- apple,nvmmu-iova
- memory-region
- '#interrupt-cells'

unevaluatedProperties: false

examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/apple-aic.h>
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
pcie0_nvmmu_window: nvmmu-window@8bee00000 {
reg = <0x8 0xbee00000 0x0 0x01200000>;
no-map;
};
};
soc {
#address-cells = <2>;
#size-cells = <2>;
pcie0: pcie@610000000 {
compatible = "apple,t8010-pcie";
device_type = "pci";
reg = <0x6 0x10000000 0x0 0x1000000>,
<0x6 0x00000000 0x0 0x8000>,
<0x6 0x00008000 0x0 0x4000>,
<0x6 0x0a000000 0x0 0x40000>,
<0x6 0x01000000 0x0 0x4000>,
<0x6 0x02000000 0x0 0x4000>,
<0x6 0x03000000 0x0 0x4000>,
<0x6 0x04000000 0x0 0x4000>,
<0x6 0x01004000 0x0 0x4000>,
<0x6 0x00010000 0x0 0x8000>;
reg-names = "config", "phy0", "phy1", "phy2",
"port0", "port1", "port2", "port3",
"nvmmu0", "pcieclk-postup";
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 276 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 279 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 288 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 289 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 290 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 291 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 292 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 293 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 294 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 295 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 296 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 297 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 298 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 299 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 300 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 301 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 302 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 303 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 304 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 305 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 306 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 307 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 308 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 309 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 310 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 311 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 312 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 313 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 314 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 315 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 316 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 317 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 318 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 319 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 272 IRQ_TYPE_EDGE_RISING>;
msi-controller;
msi-parent = <&pcie0>;
apple,msi-doorbell = <0xbffff000>;
apple,enabled-ports = <0x1>;
apple,nvmmu-iova = <0xbc000000>;
memory-region = <&pcie0_nvmmu_window>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
bus-range = <0x00 0x0f>;
ranges = <0x03000000 0x0 0xc0000000
0x7 0xc0000000 0x0 0x40000000>;
clocks = <&clkref>, <&clkref>, <&clkref>;
clock-names = "core", "aux", "ref";
power-domains = <&ps_pcie>, <&ps_pcie_aux>,
<&ps_pcie_ref>;
power-domain-names = "core", "aux", "ref";
reset-gpios = <&pinctrl_ap 12 GPIO_ACTIVE_HIGH>;
clkreq-gpios = <&pinctrl_ap 16 GPIO_ACTIVE_HIGH>;
};
};
...
117 changes: 117 additions & 0 deletions arch/arm64/boot/dts/apple/t8010-ipad7.dtsi
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* now.
*/
#include "t8010-ipad6.dtsi"

/ {
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;

pcie0_nvmmu_window: nvmmu-window@8bee00000 {
reg = <0x8 0xbee00000 0x0 0x01200000>;
no-map;
};
};

soc {
pcie0_dart0: iommu@601008000 {
compatible = "apple,t8010-dart", "apple,s5l8960x-dart";
reg = <0x6 0x01008000 0x0 0x4000>;
#iommu-cells = <1>;
interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&ps_pcie>;
apple,dma-range = <0x0 0x80000000 0x0 0x3c000000>;
};

pcie0: pcie@610000000 {
compatible = "apple,t8010-pcie";
device_type = "pci";
status = "okay";

reg = <0x6 0x10000000 0x0 0x1000000>,
<0x6 0x00000000 0x0 0x8000>,
<0x6 0x00008000 0x0 0x4000>,
<0x6 0x0a000000 0x0 0x40000>,
<0x6 0x01000000 0x0 0x4000>,
<0x6 0x02000000 0x0 0x4000>,
<0x6 0x03000000 0x0 0x4000>,
<0x6 0x04000000 0x0 0x4000>,
<0x6 0x01004000 0x0 0x4000>,
<0x6 0x00010000 0x0 0x8000>;
reg-names = "config", "phy0", "phy1", "phy2",
"port0", "port1", "port2", "port3",
"nvmmu0", "pcieclk-postup";

interrupt-parent = <&aic>;
interrupts = <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 276 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 279 IRQ_TYPE_LEVEL_HIGH>,
<AIC_IRQ 288 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 289 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 290 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 291 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 292 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 293 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 294 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 295 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 296 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 297 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 298 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 299 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 300 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 301 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 302 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 303 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 304 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 305 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 306 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 307 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 308 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 309 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 310 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 311 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 312 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 313 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 314 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 315 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 316 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 317 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 318 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 319 IRQ_TYPE_EDGE_RISING>,
<AIC_IRQ 272 IRQ_TYPE_EDGE_RISING>;

msi-controller;
msi-parent = <&pcie0>;
apple,msi-doorbell = <0xbffff000>;
apple,enabled-ports = <0x1>;
apple,nvmmu-iova = <0xbc000000>;
memory-region = <&pcie0_nvmmu_window>;

iommu-map = <0x100 &pcie0_dart0 0 1>;
iommu-map-mask = <0xff00>;

#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-controller;
bus-range = <0x00 0x0f>;
ranges = <0x03000000 0x0 0xc0000000
0x7 0xc0000000 0x0 0x40000000>;

clocks = <&clkref>, <&clkref>, <&clkref>;
clock-names = "core", "aux", "ref";
power-domains = <&ps_pcie>, <&ps_pcie_aux>,
<&ps_pcie_ref>;
power-domain-names = "core", "aux", "ref";

reset-gpios = <&pinctrl_ap 12 GPIO_ACTIVE_HIGH>,
<&pinctrl_ap 13 GPIO_ACTIVE_HIGH>,
<&pinctrl_ap 14 GPIO_ACTIVE_HIGH>,
<&pinctrl_ap 15 GPIO_ACTIVE_HIGH>;
clkreq-gpios = <&pinctrl_ap 16 GPIO_ACTIVE_HIGH>,
<&pinctrl_ap 17 GPIO_ACTIVE_HIGH>,
<&pinctrl_ap 18 GPIO_ACTIVE_HIGH>,
<&pinctrl_ap 19 GPIO_ACTIVE_HIGH>;
};
};
};
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