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August 24, 2026 07:13
…aware routing) Three fixes extracted from the production ACR image (v0.5.14-cp-layersplit-v17-patched-ropefix6, base commit 5af1f94), verified byte-identical against the deployed image: 1. utils.py (dsa_cp_round_robin_split_data): add .contiguous() to input_[indices] - Fixes aiter rope stride assertion crash when tokens % cp_size != 0 - (single-element tensor stride=[8] non-contiguous view, ropefix5) 2. deepseek_v2.py (rebuild_cp_kv_cache): .clone() before slice write - Fixes 'input tensor and written-to tensor refer to a single memory location' - CP path view-alias between k_pe/k_nope and latent_cache (ropefix4) 3. cache_aware.rs (low-cache-match policy): use smallest tree size instead of min load - cache-aware routing: prefer worker with most available cache capacity
AMD MI300X PD (Prefill-Decode) cluster operations runbook: - 2p2d topology, images (ropefix6/v17-patched/cacheaware-fix), bootstrap commands - Spot eviction recovery, worker registration, health-check tuning - Troubleshooting decision tree, image evolution table Sensitive values (API keys, public IPs, ACR name, otel endpoint) redacted to placeholders; original kept in /root/.xbot/skills/amd-ops (local only).
CjiW
marked this pull request as draft
August 24, 2026 09:00
Full diff of deployed image (ropefix6, base 5af1f94) vs main, verified byte-identical via md5 against the ACR image. Covers the AMD bring-up code that was previously missing from git history: - HiCache: hicache.cuh/relayout.cuh/staged_write_back.cuh, hicache.py, decode_hicache_mixin.py, hicache_storage.py, memory_pool_host.py - CP layersplit: cp_utils.py (+84 lines: dsa_cp_layersplit ops) - DSA: dsa_indexer.py (+11), dsa_backend.py, dsa/utils.py - PD disaggregation: conn.py, decode.py, prefill.py, pd_disaggregation_hook.py - Unified radix cache: +109 lines (tenant-aware eviction) - mooncake store, kv_cache_builder, pool_configurator, server_args (+65) Note: 7 triton_3_1_0 MI300X moe configs exist in main but were absent in the deployed image (build-time cleanup); intentionally NOT deleted here (they are valid tuned params). ropefix4/5 + cache-aware routing were committed in 2464e4a.
added 4 commits
August 24, 2026 09:51
Binary patches used by the production ACR image (ropefix6), extracted
from the deployed image and verified byte-identical (md5 0e1b8fdd...):
- patches/mooncake/engine_v3.so (67MB, LFS):
V3 mooncake engine.so, the ONLY binary patch needed for PD disaggregation.
Official engine.so segfaults on 'Tree cache initialized'; V3 works.
libasio.so + store.so identical to official (no patch needed).
Deployed via docker volume mount:
-v engine_v3.so:/opt/venv/lib/python3.10/site-packages/mooncake/engine.cpython-310-x86_64-linux-gnu.so:ro
- patches/mooncake/engine_dmabuf_patched.so (7MB, LFS): dmabuf variant
- patches/mooncake/patch_mooncake_hip_transport.sh:
disable HIP IPC transport (forces RDMA; cross-node HIP IPC segfaults)
- patches/mooncake/patch_mooncake_dmabuf.sh: dmabuf build script
- patches/mooncake/hip_approach_b.h + nvlink_allocator_approach_a.cpp:
HIP transport approach source (approach B / nvlink allocator)
- patches/v3/*.diff: aiter/layers/topk source diffs (v3 image)
.sotracked via git-lfs (git-lfs/3.5.1), forced add past *.so gitignore.
…build, LFS) Router image (cacheaware-fix) ships a separately-compiled Rust router binary different from prefill/decode images (md5 84946bbb..., 42.3MB vs 395c3a11.../36.6MB in prefill/decode). Contains the cache_aware.rs tree-size routing policy compiled in. Deployed as: /opt/venv/lib/python3.10/site-packages/sglang_router/sglang_router_rs.abi3.so Verified md5 against ACR image b200routeraca...:v0.5.14-cp-layersplit-v17-cacheaware-fix.
…ool) 318-line module imported by 8 files (dsa_backend, prefill, cache_controller, model_runner_kv_cache_mixin, kv_cache_builder, hybrid_pool_assembler, disaggregation/utils.py) — routes each global layer_id to owned or transient inner pool. Was present in deployed image (md5 485081e3) but never tracked in git; the 25-file sync in 8d55eed missed it because diff -rq only showed it as 'Only in deployed'. Verified md5 identical.
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Motivation
Sync production AMD MI300X PD (Prefill-Decode) deployment code and binaries into the fork. The production cluster (Azure VMSS, SGLang v0.5.14 + AITER, GLM-5.2 FP8) runs from ACR images built on top of
5af1f949c; this PR makes the deployment state reproducible from git, and unifies the three role images into a single image.🚀 Unified image (NEW — 2026-08-24)
The three role images previously shipped separately; they can be merged into one image since prefill/decode (Python server) and router (Rust binary) do not conflict:
...-ropefix6(prefill)b200routeraca.azurecr.io/mindverse/sglang:v0.5.14-cp-layersplit-v17-unified...-v17-patched(decode)sha256:2d7471420f60..., ~92GB)...-cacheaware-fix(router)Build method (unified v2 — REQUIRED full package replace, not just .so):
Verify inside image:
End-to-end verified 2026-08-24 (unified v2, node-0 prefill + node-4 decode+router):
/health_generate200 (1s)Role launch (same image, different entrypoint):
python -m sglang.launch_server --disaggregation-mode prefill --port 30100 ...python -m sglang.launch_server --disaggregation-mode decode --port 30200 ...python -m sglang_router.launch_router --pd-disaggregation -p <prefill> -d <decode> ...All three ship: python fixes (ropefix4/5 + 25-file AMD code + cp_layersplit_pool.py) + mooncake
engine_v3.so(md50e1b8fdd...) + routersglang_router_rs.abi3.so(cacheaware, md584946bbb...).Modifications
1. Python source fixes (verified byte-identical against deployed image)
utils.py(dsa_cp_round_robin_split_data): add.contiguous()toinput_[indices]— fixes aiter rope stride assertion crash whentokens % cp_size != 0(single-element tensor stride=[8] non-contiguous view).deepseek_v2.py(rebuild_cp_kv_cache):.clone()before slice write — fixes"input tensor and written-to tensor refer to a single memory location"(CP path view-alias betweenk_pe/k_nopeandlatent_cache).cp_layersplit_pool.py(new, 318 lines): CP layer-split KV pool, imported by 8 modules (dsa_backend, prefill, cache_controller, model_runner_kv_cache_mixin, kv_cache_builder, hybrid_pool_assembler, disaggregation/utils). Was present in deployed image (md5 485081e3) but never tracked in git.cache_aware.rs(sgl-model-gateway): low-cache-match policy uses smallest tree size (cache-aware routing), not min load.2. Binary patches (via git-lfs,
patches/)patches/mooncake/engine_v3.so(67 MB, LFS, md50e1b8fdd2d39e007b58c3e1711ec398b): the only binary patch needed for PD disaggregation. Official mooncakeengine.sosegfaults on "Tree cache initialized"; V3 image version works.libasio.so+store.soare identical to official (no patch needed).patches/mooncake/engine_dmabuf_patched.so(7 MB, LFS): dmabuf variant.patches/mooncake/sglang_router_rs_abi3_router.so(42 MB, LFS, md584946bbb...): router image's separately-compiled Rust router binary (cacheaware-fix build; prefill/decode images ship 36.6 MB395c3a11...).patches/mooncake/patch_mooncake_hip_transport.sh+patch_mooncake_dmabuf.sh: source patch scripts (see below for what they change).patches/mooncake/hip_approach_b.h+nvlink_allocator_approach_a.cpp: HIP transport approach source (approach B / nvlink allocator).3. What the mooncake patch changes (code-level)
Two issues fixed in
mooncake-transfer-engine(source in/sgl-workspace/Mooncake/mooncake-transfer-engine/src):Issue 1 — HIP IPC transport hijacks cross-node transfers → segfault
mooncakewas compiled with-DUSE_HIP=ON -DENABLE_MULTI_PROTOCOL=ON, registering both HIP IPC transport (priority=4) and RDMA transport (priority=2). Since HIP priority > RDMA, cross-node transfers wrongly picked HIP IPC — which only supports same-node — producinghipIpcOpenMemHandle failed→ segfault.Issue 2 — GPUDirect RDMA (dmabuf) not propagated to rdma_transport target
CMakeCachehadUSE_HIP_DMABUF:BOOL=ONbut the flag wasn't passed to therdma_transportcompile target, so dmabuf registration never happened.Apply + rebuild:
4. Worker role image matrix (for reference — superseded by unified image)
...-ropefix6395c3a11...36.6MB...-v17-patched395c3a11...36.6MB...-cacheaware-fix84946bbb...42.3MBNote: 7
triton_3_1_0MI300X moe configs exist inmainbut were absent in the deployed image (build-time cleanup); intentionally NOT deleted here (valid tuned params).patches/v3/*.diff(topk FP8 precision / layers LoRA aliasing / aiter LoRA residual) are B300-environment patches, NOT applied to this 1p3d deployment — kept for reference only.Accuracy Tests
shape=[1] stride=[8]crash no longer occurs (was 8× before every crash).