Fix unreadable code in logs - #3
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This was referenced Jul 10, 2026
josephnef
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Jul 12, 2026
…ernel channel/runtime obligations + quirks doc (#238) (#268) Closes the reproducible half of #238 on the reference hardware (LB-LINK BL-M8812EU2, rfe-21) and lands the issue's deliverable, `docs/8822e-quirks.md`. Everything below is hardware-validated on the two-adapter bench (8812EU ↔ 8822CU, plus the vendor kernel and an in-tree rtw88 ground as controls); reproducers ship under `tests/`. ## Root causes & fixes - **MCS4+/48M+ whole-PPDU TX corruption** (the follow-up comments' bug): two interacting halves — 1. the DPDT antenna switch was never routed to WL control (halmac pin-mux family devourer's hand-rolled MAC init skips): `REG_LED_CFG 0x4c[24]` = `BIT_DPDT_WLBT_SEL` set, `[22]` clear, applied post-coex; 2. OFDM 1SS TX must ride ONE path (kernel `txpath_1ss` semantics): `0x820=0x32` (1ss-B) at 5 GHz / `0x31` at 2.4 GHz. The old 1ss-on-both mapping interacts with the DPDT fix (MCS0 wedges). Result: MCS7 goes 0 → ~5000 clean/12 s EVM −48; full ladder MCS0/4/7/54M clean; 40 MHz 5226 @ −53; 80 MHz TX verified against an independent kernel ground (5658 frames). - **Quirk #1 (`0x41e8` path-B RX-desense) RESOLVED**: it was a downstream artifact of the same front-end mis-config, not TSSI asymmetry (`tests/eu_41e8_desense_recheck.sh`: poking the ref with RX live = −2 %, noise). The structural skip is retired — path-B OFDM TX power is controllable in TX+RX mode again (full-duplex proof: 24k RX frames + 14.3k clean MCS7 simultaneously, `tests/eu_fullduplex_pathb_check.sh`). - **RF reg `0x0` writes silently no-op'd** through the direct BB window — routed through the legacy FON port `0x1808/0x4108` per the kernel, in both halrf impls AND the radio-table loader (the vendor tables carry reg-0 entries). Verified via the TXGAPK gain-table readback (all-zero before, kernel-shaped ramps after). - **Construction-time TX-power state was clobbered by the FW power/coex H2Cs** — authoritative TXAGC re-apply now runs after them; `PAD_CTRL1[29:28]` re-asserted there too. ## Kernel channel/runtime obligations ported (systematic source diff vs `reference/rtl88x2eu`) - **Spur elimination** (14 harmonic channel/BW combos + explicit spur-free default, every switch; FastRetune declines spur hops — hop parity PASS at 20 and 40 MHz) - **CCK TX shaping filter** (per-2.4 GHz-channel, ch14 special set) - **IGI toggle after every full channel set, both variants** — fixes the intermittent post-switch RX deafness / first-cell TX wedge (CU ch6 ground liveness 5/5, EU wedge 0/6 repro) - **LCK synthesizer re-lock** on ≥4-unit thermal drift (fired live in a 22-min max-duty soak: 1.10 M clean MCS7 frames, EVM drift +3 dB) - **phydm monitor-mode dynamic mechanisms** (`PhydmRuntimeJaguar3`): FA/CCA statistics, unlinked DIG, CCK-PD type4, EDCCA tracking — with one hardware-forced deviation: the DIG floor is `0x1e`, not phydm's generic `0x1c` (at `0x1c` the 8822CU's dense-QAM RX decodes 0 of 65k MCS7 frames; `0x1e` passes 65.9k — same class as the kernel's per-IC "For HW setting" exceptions). RX-only sessions tick from a dedicated thread (register I/O on the bulk-IN event thread starves its own event loop). ## Verified non-gaps & closures - TSSI subsystem NOT needed (kernel runs thermal mode here; `0x1e7c[30]=0` under both drivers); thermal LUT already at parity; TX descriptor byte-identical (48 B). - **Matched-power TX EVM parity** (`tests/eu_matched_power_evm.sh`, refs bit-identical): MCS7 median −60 under both drivers. - **Quirk #3 (2.4 GHz TX)**: kernel parity — the module airs undecodable 2.4 GHz under BOTH drivers (in-session verified ground; 51k kernel frames → 0). README bench row corrected; not a devourer gap. - Quirks #2/#6 validated (2.4 GHz RX on ch1/6/11 + 11× 5↔2.4 band-hop cycles; `RF 0x1a` TX_CCK_IND held post-IQK in full and fast paths). ## Out of scope / follow-ups - #7 (BT-combo `0bda:e822`) and board variance: blocked on hardware (documented in the quirks doc). - 8822CU 80 MHz RX gap found during the matrix audit → tracked separately in #267. ctest 19/19 across the rebase onto current master; per-chip config subsets build (spot-checked no-Jaguar3). 🤖 Generated with [Claude Code](https://claude.com/claude-code) --------- Co-authored-by: Claude Opus 4.8 <noreply@anthropic.com>
snokvist
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Aug 30, 2026
… duplication - **Partial arm could escape teardown** (Qodo OpenIPC#4, real bug). `_ack_armed` was set after `ack::enable()` returned. That call is five register writes ending with the net_type field that actually arms the engine, and any of them can throw on a stalling device — including after the arming write reached hardware. The exception unwinds into Init()/InitWrite()'s catch, which calls Stop(); with the flag still false that teardown skipped the disarm, leaving an unowned radio auto-ACKing when teardown_power_down is off. Latch before the first write instead: a redundant disarm costs one USB round-trip, a missed one costs an unowned transmitter. - **Root CLAUDE.md carried subtree facts** (Qodo #1, OpenIPC#3). The root file is cross-cutting only, and the added parenthetical also stated a favourable measured result with its counterpart a link away rather than in the same breath. Dropped — the not-ported list is updated, and the ARQ narrative stays in src/rtl8733b/CLAUDE.md where its counterparts already sit. - **ARQ prose restated the ack_timeout_us contract** (Qodo #2). Range, clamp, default and register are doc-commented at the DeviceConfig declaration; the subtree file now points there and keeps only what is specific to this backend (the vendor 0x21 that init_wmac still writes and why, the readback, the measured values). Re-verified on hardware after the change: responder 1349/1349 ACKed at retries_mean 0.00, retarget 1348/1349, disarmed control 0.00 with retries pinned at 12; teardown disarm still holds with power-down disabled. Co-Authored-By: Claude Opus 5 (1M context) <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01VjcZRPjNtsy2mxfDkAWNpd
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