ROCm · saadrahim · May 8, 2025 · Apr 9, 2025 · Apr 9, 2025 · Apr 9, 2025
diff --git a/.wordlist.txt b/.wordlist.txt
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 mnt
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+AMDSMI
+AST
+IOD
+IODs
+amd
+amdsmi
+celerator
+chiplets
+vllm
+misconfigurations
+integrators
+hyperscaler
+lifecycle
+prem
+ASPEED
+LLC
+SVM
+TPX
+addressability
+datacenter
+programmability
+uptime
+TPX
diff --git a/docs/gpu-partitioning/images/mi300a_CPX.png b/docs/gpu-partitioning/images/mi300a_CPX.png
diff --git a/docs/gpu-partitioning/images/mi300a_NPS1.png b/docs/gpu-partitioning/images/mi300a_NPS1.png
diff --git a/docs/gpu-partitioning/images/mi300a_SPX.png b/docs/gpu-partitioning/images/mi300a_SPX.png
diff --git a/docs/gpu-partitioning/images/mi300a_TPX.png b/docs/gpu-partitioning/images/mi300a_TPX.png
diff --git a/docs/gpu-partitioning/images/mi300x_CPX.png b/docs/gpu-partitioning/images/mi300x_CPX.png
diff --git a/docs/gpu-partitioning/images/mi300x_NPS1.png b/docs/gpu-partitioning/images/mi300x_NPS1.png
diff --git a/docs/gpu-partitioning/images/mi300x_NPS4.png b/docs/gpu-partitioning/images/mi300x_NPS4.png
diff --git a/docs/gpu-partitioning/images/mi300x_SPX.png b/docs/gpu-partitioning/images/mi300x_SPX.png
diff --git a/docs/gpu-partitioning/index.rst b/docs/gpu-partitioning/index.rst
@@ -0,0 +1,64 @@
+.. meta::
+   :description: Learn how to partition AMD GPUs/APUs.
+   :keywords: AMD, GPU, APU, partitioning, ROCm, MI300X, MI300A
+
+**************************
+AMD GPU/APU Partitioning
+**************************
+
+Partitioning Overview
+^^^^^^^^^^^^^^^^^^^^^^
+
+Modern large-scale AI and HPC workloads demand fine-grained control over GPU resource allocation, memory isolation, and multi-tenant scheduling. AMD's Instinct™ MI300 series accelerators — including the MI300X GPU and MI300A APU — support flexible partitioning schemes that allow users to logically subdivide a single device into multiple independent partitions optimized for different workloads.
+
+This documentation portal serves as a centralized index for navigating the complete GPU partitioning workflow on AMD platforms. It links to detailed technical guides for each supported accelerator, including:
+
+- **Architecture deep dives** to understand partitioning capabilities.
+- **Quick start instructions** to apply compute and memory partition modes using `amd-smi`.
+- **Guide to run vLLM workload** for inference benchmarking.
+- **Troubleshooting resources** for resolving partitioning issues in production environments.
+
+Compatibility Matrix
+^^^^^^^^^^^^^^^^^^^^^^
+
+To streamline deployment planning and reduce configuration friction, we include below a **GPU Partitioning Schemes Compatibility Matrix**. This matrix outlines which combinations of **Compute Partitioning Modes** (e.g., SPX, CPX) and **Memory Partitioning Modes** (e.g., NPS1, NPS4) are validated for each supported device. It also notes any **minimum ROCm driver version requirements** necessary to enable specific configurations.
+
+.. important::
+   **New to partitioning modes?** Before using the compatibility matrix, it's essential to understand the core concepts of **Compute Partitioning Modes** (SPX, CPX, TPX) and **Memory Partitioning Modes** (NPS1, NPS4). These modes determine how compute and memory resources are logically divided across a single device.
+
+   See our detailed overview here: 
+    - :ref:`MI300X Compute Partitioning <mi300x_compute-partitioning>` / :ref:`MI300A Compute Partitioning <mi300a_compute-partitioning>`
+    - :ref:`MI300X Memory Partitioning <mi300x_memory-partitioning>` / :ref:`MI300A Memory Partitioning <mi300a_memory-partitioning>`
+
+By consolidating this matrix on the index page, users can quickly evaluate platform capabilities and navigate to device-specific documentation with full awareness of what is supported on their hardware and software stack.
+
+.. list-table:: GPU Partitioning Schemes Compatibility Matrix
+  :header-rows: 1
+  :widths: 20 20 20 20 20
+
+  * - Instinct GPUs
+    - SPX + NPS1
+    - TPX + NPS1
+    - CPX + NPS1
+    - CPX + NPS4
+  * - MI300X
+    - ✅
+    - NA
+    - 
+    - ✅ (ROCm 6.4)
+  * - MI300A
+    - ✅
+    - ✅ (ROCm 6.3)
+    - ✅ (ROCm 6.4)
+    - NA
+
+.. note::
+    The compatibility matrix is a living document and will be updated as new ROCm releases and device capabilities are validated. Users are encouraged to check back frequently for the latest information.
+
+Device Documentation
+^^^^^^^^^^^^^^^^^^^^^
+
+- :doc:`AMD Instinct MI300X GPU <mi300x/index>` — Includes guidance for MI300X GPU-specific partitioning, architecture, System compatibility, and running vLLM inference.
+- :doc:`AMD Instinct MI300A APU <mi300a/index>` — Includes guidance for APU-specific partitioning, architecture, System compatibility, and running vLLM inference.
+
+We recommend users start with this index page to assess compatibility, then follow device-specific documentation to implement and validate GPU partitioning configurations in their own clusters or platforms.
diff --git a/docs/gpu-partitioning/mi300a/index.rst b/docs/gpu-partitioning/mi300a/index.rst
@@ -0,0 +1,28 @@
+.. meta::
+   :description: AMD Instinct MI300A APU
+   :keywords: AMD, MI300A, APU, CPU-GPU, Instinct, Overview
+
+*******************************************
+AMD Instinct MI300A APU
+*******************************************
+
+The AMD Instinct™ MI300A APU (Accelerated Processing Unit) is a groundbreaking compute platform that fuses AMD EPYC™ CPU cores with CDNA™ 3 GPU architecture into a single, unified package. Purpose-built for data-intensive AI, HPC, and scientific computing workloads, the MI300A offers unprecedented levels of memory bandwidth, compute density, and energy efficiency — all through a cohesive CPU-GPU heterogeneous system.
+
+As the world’s first data center APU based on **advanced chiplet packaging**, MI300A breaks traditional boundaries by enabling shared memory between the CPU and GPU, reducing latency and eliminating redundant data transfers. This guide provides an in-depth reference for developers, system architects, and platform integrators working with MI300A systems — from configuration and partitioning to memory access models and workload deployment.
+
+Key technical highlights of the MI300A platform include:
+
+- **24 Zen 4 CPU cores** integrated with **228 CDNA 3 CUs**, all sharing a unified addressable HBM memory pool.
+- Up to **128 GB of unified HBM3 memory**, accessible by both CPU and GPU without the need for explicit memory copies.
+- **Advanced GPU partitioning** support (SPX, CPX, TPX) enabling workload isolation, fine-grained scheduling, and resource optimization.
+- Hardware-accelerated **coherent shared memory**, enabling low-latency CPU-GPU communication for tightly coupled compute models.
+- Full compatibility with the **ROCm 6.x software stack**, including HIP, OpenMP offload, and leading AI/ML libraries.
+
+This guide is structured to help users get the most out of MI300A across a wide range of applications:
+
+- :doc:`Overview <overview>` — Deep dive into MI300A architecture, APU topology, and compute/memory partitioning models.
+- :doc:`Requirements <requirements>` — Platform setup, BIOS/kernel configuration, ROCm compatibility matrix, and supported distros.
+- :doc:`Quick Start Guide <quick-start-guide>` — Walkthrough for bringing up MI300A systems and configuring partitions using `amd-smi`.
+- :doc:`Troubleshooting <troubleshooting>` — Diagnosing common errors, partition conflicts, and optimizing workload placement.
+
+Whether you are deploying the MI300A in an exascale supercomputer or using it to accelerate simulation, AI, or analytics workloads, this documentation serves as your go-to reference for maximizing performance, interoperability, and development agility.