Silicon Badgers technical projects

Start with the shared introduction, then choose RTL or verification.

Read	What is there
CAE setup	Connect, get the repository, run VCS, and view waveforms.
Shared introduction	Digital logic, waveform exercises, SystemVerilog, and the PE project.
RTL track	Build the systolic array design.
Verification track	Develop tests, follow the verification plan, and complete the testbench.

Each page has a short contents list for jumping between sections. Links to code open the relevant file and line range.

First run

Follow CAE setup, then run from the repository root on CAE:

make check
module load synopsys/suite
synopsys-run
make smoke

make day1 simulates the supplied gates, full adder, mux, and slide 21 waveform expressions, checks their outputs, and writes build/day1/waves.vcd for viewing in GTKWave.

make pe runs processing element (PE) testbench; the template RTL is expected to fail until you implement it.

Completion checkpoints

Exercises between these milestones are self-paced practice.

Checkpoint	Applies to	Completion check
PE	Shared introduction	The PE passes all seven configurations of the supplied acceptance suite.
Matmul	RTL	The 2×2 implementation computes complete matrix products correctly.
Systolic array	RTL	The completed array handles the agreed configurations and control behavior.
Testbench completion	Verification	The completed testbench checks requirements and detects design errors.

The array and extended testbench are still planned; their guides describe what to build next. For repository changes, see Contributing.