Arm64 R2R: fold adrp+add+ldr into adrp+ldr[#:lo12:] by EgorBo · Pull Request #129589 · dotnet/runtime

EgorBo · 2026-06-18T18:45:41Z

On Arm64 R2R (and runtime JIT), a value load through a relocatable indirection cell emits adrp + add + ldr. The page offset can be folded directly into the ldr via a new PAGEOFFSET_12L relocation, saving one instruction per access. This is what x64 gets for free with RIP-relative addressing, and the managed AOT object-writer side already supported 12L — only RyuJIT never emitted it.

For example:

public static void Test()
{
    Console.WriteLine("hello");
}

Before → after (Arm64 R2R):

 adrp x0, [HIGH RELOC]              adrp x0, [HIGH RELOC]
 add  x0, x0, [LOW RELOC]     →     ldr  x0, [x0, [LOW RELOC]]   ← folded
 ldr  x0, [x0]                      ldr  x0, [x0]
 ldr  x0, [x0]

-2.1 MB on libraries.crossgen SPMI collection.

System.Private.CoreLib.dll (R2R): 18032 KB -> 17840 KB (-192 KB)

Add an Arm64 PAGEOFFSET_12L relocation so a value load through a relocatable cell folds the page offset into the ldr, saving one instruction per access (R2R and runtime JIT). Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

dotnet-policy-service · 2026-06-18T18:47:06Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
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Copilot

Pull request overview

This PR adds a new Arm64 relocation kind (ARM64_PAGEOFFSET_12L) and teaches RyuJIT (and supporting infrastructure) to fold a relocatable adrp + add + ldr sequence into adrp + ldr [#:lo12:], saving an instruction for common indirection-cell value loads in R2R/relocatable codegen.

Changes:

Add CorInfoReloc::ARM64_PAGEOFFSET_12L and wire it through the JIT/EE boundary (including a JIT/EE GUID bump).
Introduce GetArm64Rel12Ldr / PutArm64Rel12Ldr helpers and use them in VM and SuperPMI relocation fixups.
Implement an emitter peephole to remove the relocatable add and emit an ldr carrying the new relocation.

Reviewed changes

Copilot reviewed 12 out of 12 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
src/coreclr/vm/jitinterface.cpp	Handles the new `ARM64_PAGEOFFSET_12L` relocation in the runtime relocation fixer.
src/coreclr/utilcode/util.cpp	Adds LDR-specific rel12 extract/deposit helpers for Arm64.
src/coreclr/tools/superpmi/superpmi-shared/spmiutil.h	Declares `PutArm64Rel12Ldr` for SuperPMI’s relocation patching utilities.
src/coreclr/tools/superpmi/superpmi-shared/spmiutil.cpp	Implements `PutArm64Rel12Ldr` in SuperPMI’s local copy of utilcode helpers.
src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp	Adds stringification and application support for `ARM64_PAGEOFFSET_12L` during replay normalization.
src/coreclr/tools/Common/JitInterface/CorInfoTypes.cs	Extends the managed mirror of `CorInfoReloc` with `ARM64_PAGEOFFSET_12L`.
src/coreclr/tools/Common/JitInterface/CorInfoImpl.cs	Maps `ARM64_PAGEOFFSET_12L` to the object-writer relocation type.
src/coreclr/jit/emitarm64.h	Declares `TryFoldPageOffsetIntoLdr` helper for the emitter peephole.
src/coreclr/jit/emitarm64.cpp	Implements folding logic and records the new relocation for the folded `ldr`.
src/coreclr/inc/utilcode.h	Declares `GetArm64Rel12Ldr` / `PutArm64Rel12Ldr` helpers.
src/coreclr/inc/jiteeversionguid.h	Bumps the JIT/EE interface GUID due to the new relocation enum value.
src/coreclr/inc/corinfo.h	Adds `ARM64_PAGEOFFSET_12L` to the native `CorInfoReloc` enum.

Address review feedback: the predicate gates on EA_SIZE == EA_8BYTE in a general register, which includes GCREF/BYREF; "integer loads" was misleading. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Copilot

Pull request overview

Copilot reviewed 12 out of 12 changed files in this pull request and generated 1 comment.

EgorBo · 2026-06-19T14:09:01Z

/azp list

EgorBo · 2026-06-19T14:09:54Z

/azp run runtime-coreclr outerloop, runtime-coreclr crossgen2, runtime-coreclr r2r

azure-pipelines · 2026-06-19T14:10:12Z

Azure Pipelines successfully started running 3 pipeline(s).

Copilot

Pull request overview

Copilot reviewed 12 out of 12 changed files in this pull request and generated 1 comment.

EgorBo · 2026-06-19T17:40:04Z

PTAL @dotnet/jit-contrib all outerloop pipelines passed

EgorBo · 2026-06-22T19:45:18Z

PTAL @dhartglassMSFT @dotnet/jit-contrib
for VM side @jkotas @MichalStrehovsky?

Copilot

Pull request overview

Copilot reviewed 12 out of 12 changed files in this pull request and generated no new comments.

tannergooding

LGTM. Just a couple questions about handling other scenarios (possibly just in the future).

EgorBo · 2026-06-26T10:50:35Z

/ba-g timeouts

…9966) Fixes #129936. PR #129589 added an Arm64 fold of `adrp+add+ldr` into `adrp+ldr[#:lo12:]` via a 64-bit `PAGEOFFSET_12L` reloc (`R_AARCH64_LDST64_ABS_LO12_NC`). That reloc encodes the offset scaled by 8, so the target must be 8-byte aligned. In R2R the relocatable loads always go through pointer-aligned indirection cells, but NativeAOT can fold a direct 64-bit load of byte-packed frozen data (4-byte aligned), which `ld.lld` rejects: ``` ld.lld : error : improper alignment for relocation R_AARCH64_LDST64_ABS_LO12_NC: 0x74A52C is not aligned to 8 bytes ``` The fold is purely a size optimization, so this restricts it to non-NativeAOT and falls back to the always-safe `adrp+add+ldr`. Validation (SPMI, linux-arm64): - `benchmarks.run` (R2R, ~427K contexts): **0 asm diffs** — the win is preserved. - `smoke_tests.nativeaot` (18891 ctx): clean replay, no diffs. --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>

On Arm64 R2R (and runtime JIT), a value load through a relocatable indirection cell emits `adrp + add + ldr`. The page offset can be folded directly into the `ldr` via a new `PAGEOFFSET_12L` relocation, saving one instruction per access. This is what x64 gets for free with RIP-relative addressing, and the managed AOT object-writer side already supported `12L` — only RyuJIT never emitted it. For example: ```cs public static void Test() { Console.WriteLine("hello"); } ``` Before → after (Arm64 R2R): ```asm adrp x0, [HIGH RELOC] adrp x0, [HIGH RELOC] add x0, x0, [LOW RELOC] → ldr x0, [x0, [LOW RELOC]] ← folded ldr x0, [x0] ldr x0, [x0] ldr x0, [x0] ``` **-2.1 MB** on libraries.crossgen SPMI collection. System.Private.CoreLib.dll (R2R): 18032 KB -> 17840 KB (**-192 KB**) --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

…9966) Fixes #129936. PR #129589 added an Arm64 fold of `adrp+add+ldr` into `adrp+ldr[#:lo12:]` via a 64-bit `PAGEOFFSET_12L` reloc (`R_AARCH64_LDST64_ABS_LO12_NC`). That reloc encodes the offset scaled by 8, so the target must be 8-byte aligned. In R2R the relocatable loads always go through pointer-aligned indirection cells, but NativeAOT can fold a direct 64-bit load of byte-packed frozen data (4-byte aligned), which `ld.lld` rejects: ``` ld.lld : error : improper alignment for relocation R_AARCH64_LDST64_ABS_LO12_NC: 0x74A52C is not aligned to 8 bytes ``` The fold is purely a size optimization, so this restricts it to non-NativeAOT and falls back to the always-safe `adrp+add+ldr`. Validation (SPMI, linux-arm64): - `benchmarks.run` (R2R, ~427K contexts): **0 asm diffs** — the win is preserved. - `smoke_tests.nativeaot` (18891 ctx): clean replay, no diffs. --------- Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com> Co-authored-by: Jakob Botsch Nielsen <Jakob.botsch.nielsen@gmail.com>

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github-actions Bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Jun 18, 2026

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Comment thread src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp

Comment thread src/coreclr/jit/emitarm64.cpp Outdated

EgorBo and others added 2 commits June 18, 2026 21:05

Clarify fold applies to general-register (incl. GCREF/BYREF) loads

1c81ec5

Address review feedback: the predicate gates on EA_SIZE == EA_8BYTE in a general register, which includes GCREF/BYREF; "integer loads" was misleading. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>

Update emitarm64.cpp

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Merge branch 'main' into arm64-r2r-fold-pageoffset-ldr

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build-analysis Bot mentioned this pull request Jun 19, 2026

[android] Android.Device_Emulator.JIT.Test failing on emulators with CoreCLR #112633

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The Operation will be canceled. The next steps may not contain expected logs. dotnet/dnceng#3008

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[ci-scan] Test failure: X509Certificate2CollectionRemoveRangeArray under crossgen2 R2R (recurrence) #129576

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Merge branch 'main' into arm64-r2r-fold-pageoffset-ldr

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Assertion failed: new_time >= loop->time in Component Governance Detection dotnet/dnceng#6510

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Merge branch 'main' into arm64-r2r-fold-pageoffset-ldr

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Intermittent build failure in AfterSourceBuild: "Could not write state file" #76488

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slow macOS - "##[error]The job running on agent Azure Pipelines 9 ran longer than the maximum time of 60 minutes." dotnet/dnceng#1883

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browser-wasm linux Release LibraryTests queues timing out #117974

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Merge branch 'main' into arm64-r2r-fold-pageoffset-ldr

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[main] Source code updates from dotnet/runtime dotnet/dotnet#7441

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[ci-scan] Build break: NativeAOT linker alignment error in PhysicalPromotion test (arm64) #129936

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EgorBo mentioned this pull request Jun 29, 2026

Arm64: don't fold ldr page offset (PAGEOFFSET_12L) for NativeAOT #129966

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[aw] No-Op Runs #129501

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[aw] No-Op Runs #130179

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