[LoongArch64] Add atomic instruction implementation for LoongArch64

[lawn123]

Add atomic instruction for LoongArch64. Supports atomic instructions on ISA1.0 and ISA1.1
Implementation of #122745.

[lawn123]

Hi @shushanhf @LuckyXu-HF @jakobbotsch @jkotas could you please review this PR? Thanks.

[jkotas]

How does Exchange work for int and long that it is missing here?

[lawn123]

For int and long types Exchange supports both V1.0 and V1.1.

[lawn123]

@jkotas Is there anything else that needs to be modified in this PR？

[jkotas]

@dotnet/jit-contrib This is ready for review

[MichalPetryka]

When this is merged, do we want to make those must expand on all platforms? I can revive my PR for ARM32 but it seems X86 would need 64bit handled too, not sure how much work would that be. (maybe a task for copilot to see?) @jkotas

[jkotas]

do we want to make those must expand on all platforms? I can revive my PR for ARM32 but it seems X86 would need 64bit handled too, not sure how much work would that be. (maybe a task for copilot to see?) @jkotas

Optimizing x86 or Arm32 is not a priority for us. If somebody from the codegen team wants to volunteer to review x86 or Arm32 specific optimizations and deal with the fallout, I won't stop them, but I am not spending my time on it.

[github-actions]

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[github-actions]

Holistic Review

Motivation: Justified. LoongArch64 gained hardware atomic instructions (AMSWAP/AMADD/AMAND/AMOR in ISA1.0 and byte/halfword AM*.B/.H plus AMCAS in ISA1.1). Previously the JIT left Interlocked codegen as NYI and fell back to LL/SC or managed emulation. Wiring up the real atomic instructions is a legitimate CQ improvement, and the author's benchmark shows ~1.2x speedups on small-type CompareExchange.

Approach: Sound and consistent with the codebase. The change follows the established RISCV64/ARM64 pattern end-to-end: a new LoongArch64 ISA arch with two feature sets (LAM_BH, LAM_CAS) threaded through InstructionSetDesc.txt, the R2R/JIT-EE enums, CLR/JIT config knobs, minipal_getcpufeatures CPUCFG probing, NativeAOT g_cpuFeatures, the System.Runtime.Intrinsics.LoongArch.LAM intrinsic surface, and JIT importer/lowering/LSRA/codegen/emit. Runtime capability is detected dynamically with a correct LL/SC fallback when LAM_CAS is unavailable, and small-type paths throw PlatformNotSupported/fall back to managed emulation when LAM_BH is unavailable.

Summary: ⚠️ Needs Human Review. The structure is correct and mirrors proven patterns, but this is target-specific codegen that only exercises on LoongArch64 hardware/CI, so a maintainer with LA64 expertise should confirm the atomic instruction encodings, memory-ordering (_db barrier variants vs. explicit instGen_MemoryBarrier), and the LL/SC retry loop. Also note the new internal LAM/LAM.BH/LAM.CAS types are non-public intrinsics (no ref/ public API surface), so no API review is required. One low-severity defensive-coding suggestion is filed inline; the open maintainer question about whether the hand-rolled small-type emulation is worth the added codegen complexity (vs. only expanding when LAM_CAS/LAM_BH is present) should be resolved before merge.

---

Detailed Findings

⚠️ Codegen — small-type XCHG defensive gap

See the inline comment on genLockedInstructions (src/coreclr/jit/codegenloongarch64.cpp). The small-type GT_XCHG branch emits nothing if LAM_BH is absent, leaving targetReg undefined. It is unreachable given the importer gating, but an assert/unreached() would make the invariant explicit and match the style already used in genCodeForCmpXchg.

💡 Consistency — minor comment/style nits already raised by maintainers

• clrconfigvalues.h: the EnableLoongArch64LAM_CAS description still reads LAM_BH+ (copy/paste); it should describe LAM_CAS. Already flagged by a maintainer.
• cpufeatures.c: the local LAM_BH/LAM_CAS #defines and the world/cpucfg naming are a bit ad hoc; consider a comment referencing the CPUCFG word index (word 2, bits for AMCAS/AM*.B.H) for future readers. Non-blocking.

✅ ISA plumbing — correct and complete

The InstructionSetDesc.txt additions (R2R bits 94/95, NEXT_AVAILABLE_R2R_BIT = 96), hwintrinsicIsaRangeArray, ReadyToRunInstructionSetHelper, HardwareIntrinsicHelpers, InstructionSetHelpers optimistic set, and methodtablebuilder.cpp namespace mapping are all internally consistent with each other and with how other arches register feature sets. The jiteeversionguid.h bump is present as required for a JIT-EE interface change.

Note

This review was generated by this repository's Holistic Review agentic workflow to complement the built-in Copilot review.

Generated by Holistic Review · 228.3 AIC · ⌖ 15.3 AIC · ⊞ 10K

[github-actions]

💡 In this small-type GT_XCHG branch, if InstructionSet_LAM_BH is not supported the if is skipped, ins remains INS_none, and no instruction is emitted at all — targetReg is left undefined and the swap silently doesn't happen. In practice this path is unreachable because impIntrinsic only expands small-type Exchange when LAM_BH is available (otherwise it falls back to the managed impl or throws PlatformNotSupported), so this is defensive rather than a live bug. Still, consider adding an else { unreached(); } / assert(HasInstructionSet(InstructionSet_LAM_BH)) before the block so an invariant violation fails loudly instead of emitting a silent no-op. This mirrors the explicit asserts you already added in genCodeForCmpXchg.

[lawn123]

HI @jakobbotsch could you please review this PR when you have time.

[github-actions]

Holistic Review

Motivation: Unchanged and still justified. LoongArch64 gained hardware atomic instructions (AMSWAP/AMADD/AMAND/AMOR in ISA1.0 and byte/halfword AM*.B/.H plus AMCAS in ISA1.1). Previously the JIT left Interlocked codegen as NYI and fell back to LL/SC or managed emulation. Wiring up the real atomic instructions is a legitimate CQ improvement.

Approach: Unchanged and sound. The change follows the established RISCV64/ARM64 pattern end-to-end: a new LoongArch64 ISA arch with two feature sets (LAM_BH, LAM_CAS) threaded through InstructionSetDesc.txt, the R2R/JIT-EE enums, CLR/JIT config knobs, minipal_getcpufeatures CPUCFG probing, NativeAOT g_cpuFeatures, the System.Runtime.Intrinsics.LoongArch.LAM intrinsic surface, and JIT importer/lowering/LSRA/codegen/emit. Runtime capability is detected dynamically with a correct LL/SC fallback when LAM_CAS is unavailable.

Summary: ⚠️ Needs Human Review (verdict unchanged). Since the prior review the PR was rebased onto a newer main; the 12 PR commits are byte-identical in the range-diff. The only incremental content changes are mechanical and correct rebase artifacts: (1) the JIT-EE version GUID in jiteeversionguid.h was regenerated, and (2) the R2R instruction-set bit numbering for LAM_BH/LAM_CAS was shifted from 94/95 to 95/96 to avoid colliding with the upstream-added Zicond=94. I verified this renumbering is internally consistent across readytoruninstructionset.h, ReadyToRunInstructionSet.cs, CorInfoInstructionSet.cs, and ReadyToRunInstructionSetHelper.cs at the current head. No new actionable findings arise from the incremental changes. The target-specific codegen concerns from the initial review (atomic encodings, _db memory-ordering variants, the LL/SC retry loop, and the small-type emulation complexity question) remain and still warrant confirmation by a maintainer with LA64 expertise; those are in unchanged code and are not re-raised as new findings here.

---

Assessment History

• review 4730679920 reviewed commit 02f0815b93a109f8d85b019820d18061feca9576 with verdict ⚠️ Needs Human Review. Current verdict is ⚠️ Needs Human Review — unchanged. The motivation, approach, and risk assessment are all unchanged; the intervening rebase produced only a JIT-EE GUID regeneration and a rebase-driven R2R bit renumbering, neither of which alters the PR's behavior or risk.

Detailed Findings

No new actionable findings in the incremental (rebase) scope. The prior review's inline suggestion and open maintainer questions still apply to the unchanged PR patches.

Note

This review was generated by this repository's Holistic Review agentic workflow to complement the built-in Copilot review.

Generated by Holistic Review · 69.1 AIC · ⌖ 14.8 AIC · ⊞ 10K

[tannergooding]

@lawn123 could you fix the jit-format failure? That one is at the very least a blocker.

[lawn123]

@lawn123 could you fix the jit-format failure? That one is at the very least a blocker.

Updated.

[github-actions]

Holistic Review

Motivation: Unchanged and still justified. LoongArch64 gained hardware atomic instructions (AMSWAP/AMADD/AMAND/AMOR in ISA1.0 and byte/halfword AM*.B/.H plus AMCAS in ISA1.1). Previously the JIT left Interlocked codegen as NYI and fell back to LL/SC or managed emulation. Wiring up the real atomic instructions is a legitimate CQ improvement.

Approach: Unchanged and sound. The change follows the established RISCV64/ARM64 pattern end-to-end: a new LoongArch64 ISA arch with two feature sets (LAM_BH, LAM_CAS) threaded through InstructionSetDesc.txt, the R2R/JIT-EE enums, CLR/JIT config knobs, minipal_getcpufeatures CPUCFG probing, NativeAOT g_cpuFeatures, the System.Runtime.Intrinsics.LoongArch.LAM intrinsic surface, and JIT importer/lowering/LSRA/codegen/emit. Runtime capability is detected dynamically with a correct LL/SC fallback when LAM_CAS is unavailable.

Summary: ⚠️ Needs Human Review (verdict unchanged). The only incremental change since the prior review is a single new commit (534fe40e, "fix jit-format failure") that mechanically reflows two lines in src/coreclr/jit/rangecheck.h to satisfy jit-format's column/wrapping rules. It is a pure whitespace/formatting change with no behavioral effect: the r1StraddlesZero/r2StraddlesZero computations and the signedEndpointOverflows guard are logically identical to before, just re-wrapped. The 12 previously-reviewed PR commits are byte-identical in the range-diff and the merge base is unchanged. No new actionable findings arise from this incremental change. The target-specific codegen concerns from the initial review (atomic encodings, _db memory-ordering variants, the LL/SC retry loop, and the small-type emulation complexity question) remain in unchanged code and still warrant confirmation by a maintainer with LA64 expertise; they are not re-raised as new findings here.

---

Assessment History

• review 4730679920 reviewed commit 02f0815b93a109f8d85b019820d18061feca9576 with verdict ⚠️ Needs Human Review. Current verdict is ⚠️ Needs Human Review — unchanged. Motivation, approach, and risk assessment are all unchanged; subsequent changes are a rebase and a formatting-only commit that do not alter behavior or risk.
• review 4732014090 reviewed commit 9620eb16ca9a2724e3df3b3245ea836f2ac82151 with verdict ⚠️ Needs Human Review. Current verdict is ⚠️ Needs Human Review — unchanged. The only new content since that review is the jit-format whitespace reflow in rangecheck.h, which has no behavioral impact.

Detailed Findings

No new actionable findings in the incremental scope. The sole incremental change is a jit-format whitespace reflow in src/coreclr/jit/rangecheck.h. The prior review's inline suggestion and open maintainer questions still apply to the unchanged PR patches.

Note

This review was generated by this repository's Holistic Review agentic workflow to complement the built-in Copilot review.

Generated by Holistic Review · 51.7 AIC · ⌖ 15.7 AIC · ⊞ 10K