[RISC-V] Allow building the runtime assembly without the F/D, A and C extensions

src/coreclr/debug/di/riscv64/floatconversion.S

@@ -7,6 +7,8 @@
 //     input: (in A0) the address of the ULONGLONG to be converted to a double
 //     output: the double corresponding to the ULONGLONG input value
 LEAF_ENTRY FPFillR8, .TEXT
+#if __riscv_flen >= 64
         fld  fa0, 0(a0)
+#endif
         ret
 LEAF_END FPFillR8, .TEXT

src/coreclr/nativeaot/Runtime/riscv64/ExceptionHandling.S

@@ -31,6 +31,7 @@
     .endif
 
     // Safely using available registers for floating-point saves
+#if __riscv_flen >= 64
     fsd  fs0, 0x10(sp)
     fsd  fs1, 0x18(sp)
     fsd  fs2, 0x20(sp)
@@ -43,6 +44,7 @@
     fsd  fs9, 0x58(sp)
     fsd  fs10, 0x60(sp)
     fsd  fs11, 0x68(sp)
+#endif
 
     PROLOG_SAVE_REG_PAIR_INDEXED  fp, ra, 0x78
 
@@ -140,6 +142,7 @@
         // Load FP preserved registers
         //
         addi t3, \regdisplayReg, OFFSETOF__REGDISPLAY__F   // Base address of floating-point registers
+#if __riscv_flen >= 64
         fld  fs0,  0x40(t3)                                // Load fs0
         fld  fs1,  0x48(t3)                                // Load fs1
         fld  fs2,  0x90(t3)                                // Load fs2
@@ -152,6 +155,7 @@
         fld  fs9,  0xc8(t3)                                // Load fs9
         fld  fs10, 0xd0(t3)                                // Load fs10
         fld  fs11, 0xd8(t3)                                // Load fs11
+#endif
 
     .endm
 
@@ -188,6 +192,7 @@
 
         // Save floating-point registers
         addi  t3, \regdisplayReg, OFFSETOF__REGDISPLAY__F
+#if __riscv_flen >= 64
         fsd  fs0,  0x40(t3)
         fsd  fs1,  0x48(t3)
         fsd  fs2,  0x90(t3)
@@ -200,6 +205,7 @@
         fsd  fs9,  0xc8(t3)
         fsd  fs10, 0xd0(t3)
         fsd  fs11, 0xd8(t3)
+#endif
 
 .endm
 
@@ -474,6 +480,7 @@ LOCAL_LABEL(NotHijacked):
         ALLOC_CALL_FUNCLET_FRAME 0x90
 
         // Save floating-point registers
+#if __riscv_flen >= 64
         fsd  fs0,  0x00(sp)
         fsd  fs1,  0x08(sp)
         fsd  fs2,  0x10(sp)
@@ -486,6 +493,7 @@ LOCAL_LABEL(NotHijacked):
         fsd  fs9,  0x48(sp)
         fsd  fs10, 0x50(sp)
         fsd  fs11, 0x58(sp)
+#endif
 
         // Save integer registers
         sd  a0, 0x60(sp)    // Save a0 to a3
@@ -511,7 +519,14 @@ LOCAL_LABEL(NotHijacked):
         addi  t3, a5, OFFSETOF__Thread__m_ThreadStateFlags
 
         addiw  a6, zero, -17  // Mask value (0xFFFFFFEF)
+#ifdef __riscv_atomic
         amoand.w  a4, a6, (t3)
+#else
+        // No A extension: non-atomic read-modify-write.
+        lw   a4, (t3)
+        and  a4, a4, a6
+        sw   a4, (t3)
+#endif
 
         // Set preserved regs to the values expected by the funclet
         RESTORE_PRESERVED_REGISTERS a2
@@ -593,6 +608,7 @@ LOCAL_LABEL(DonePopping):
         ALLOC_CALL_FUNCLET_FRAME 0x80
 
         // Save floating-point registers
+#if __riscv_flen >= 64
         fsd  fs0,  0x00(sp)
         fsd  fs1,  0x08(sp)
         fsd  fs2,  0x10(sp)
@@ -605,6 +621,7 @@ LOCAL_LABEL(DonePopping):
         fsd  fs9,  0x48(sp)
         fsd  fs10, 0x50(sp)
         fsd  fs11, 0x58(sp)
+#endif
 
         // Save integer registers
         sd a0, 0x60(sp)  // Save a0 to 0x60
@@ -623,7 +640,14 @@ LOCAL_LABEL(DonePopping):
         // Set the DoNotTriggerGc flag
         addi  t3, a2, OFFSETOF__Thread__m_ThreadStateFlags
         addiw  a3, zero, -17  // Mask value (0xFFFFFFEF)
+#ifdef __riscv_atomic
         amoand.w  a4, a3, (t3)
+#else
+        // No A extension: non-atomic read-modify-write.
+        lw   a4, (t3)
+        and  a4, a4, a3
+        sw   a4, (t3)
+#endif
 
         // Restore preserved registers
         RESTORE_PRESERVED_REGISTERS a1
@@ -646,9 +670,17 @@ LOCAL_LABEL(DonePopping):
 
         addi  t3, a2, OFFSETOF__Thread__m_ThreadStateFlags
         addiw  a3, zero, 16  // Mask value (0x10)
+#ifdef __riscv_atomic
         amoor.w  a1, a3, (t3)
+#else
+        // No A extension: non-atomic read-modify-write.
+        lw   a1, (t3)
+        or   a1, a1, a3
+        sw   a1, (t3)
+#endif
 
         // Restore floating-point registers
+#if __riscv_flen >= 64
         fld  fs0,  0x00(sp)
         fld  fs1,  0x08(sp)
         fld  fs2,  0x10(sp)
@@ -661,6 +693,7 @@ LOCAL_LABEL(DonePopping):
         fld  fs9,  0x48(sp)
         fld  fs10, 0x50(sp)
         fld  fs11, 0x58(sp)
+#endif
 
         // Free call funclet frame
         FREE_CALL_FUNCLET_FRAME 0x80
@@ -685,6 +718,7 @@ LOCAL_LABEL(DonePopping):
 
     NESTED_ENTRY RhpCallFilterFunclet, _TEXT, NoHandler
         ALLOC_CALL_FUNCLET_FRAME 0x60
+#if __riscv_flen >= 64
         fsd  fs0,  0x00(sp)
         fsd  fs1,  0x08(sp)
         fsd  fs2,  0x10(sp)
@@ -697,6 +731,7 @@ LOCAL_LABEL(DonePopping):
         fsd  fs9,  0x48(sp)
         fsd  fs10, 0x50(sp)
         fsd  fs11, 0x58(sp)
+#endif
 
         ld  t3, OFFSETOF__REGDISPLAY__pFP(a2)
         ld  fp, 0(t3)
@@ -709,6 +744,7 @@ LOCAL_LABEL(DonePopping):
 
     ALTERNATE_ENTRY RhpCallFilterFunclet2
 
+#if __riscv_flen >= 64
         fld  fs0,  0x00(sp)
         fld  fs1,  0x08(sp)
         fld  fs2,  0x10(sp)
@@ -721,6 +757,7 @@ LOCAL_LABEL(DonePopping):
         fld  fs9,  0x48(sp)
         fld  fs10, 0x50(sp)
         fld  fs11, 0x58(sp)
+#endif
 
         FREE_CALL_FUNCLET_FRAME 0x60
         EPILOG_RETURN
@@ -774,7 +811,14 @@ LOCAL_LABEL(DonePopping):
         addi  t3, a5, OFFSETOF__Thread__m_ThreadStateFlags
 
         addiw  a6, zero, -17  // Mask value (0xFFFFFFEF)
+#ifdef __riscv_atomic
         amoand.w  a4, t3, a6
+#else
+        // No A extension: non-atomic read-modify-write.
+        lw   a4, (t3)
+        and  a4, a4, a6
+        sw   a4, (t3)
+#endif
 
         // set preserved regs to the values expected by the funclet
         RESTORE_PRESERVED_REGISTERS a2

src/coreclr/nativeaot/Runtime/riscv64/GcProbe.S

@@ -39,8 +39,10 @@
     sd  a2, 0x90(sp)
 
     # Save the FP return registers
+#if __riscv_flen >= 64
     fsd  fa0, 0x98(sp)
     fsd  fa1, 0xa0(sp)
+#endif
     # Slot at sp+0xa8 is alignment padding
 
     # Perform the rest of the PInvokeTransitionFrame initialization.
@@ -64,8 +66,10 @@
     ld  a2, 0x90(sp)
 
     // Restore the FP return registers
+#if __riscv_flen >= 64
     fld  fa0, 0x98(sp)
     fld  fa1, 0xa0(sp)
+#endif
 
     // Restore callee saved registers
     EPILOG_RESTORE_REG_PAIR s1, s2,  0x20

src/coreclr/nativeaot/Runtime/riscv64/UniversalTransition.S

@@ -89,6 +89,7 @@
         PROLOG_SAVE_REG_PAIR_INDEXED fp, ra, STACK_SIZE
 
         # Floating point registers
+#if __riscv_flen >= 64
         fsd         fa0, FLOAT_ARG_OFFSET(sp)
         fsd         fa1, FLOAT_ARG_OFFSET + 0x08(sp)
         fsd         fa2, FLOAT_ARG_OFFSET + 0x10(sp)
@@ -97,6 +98,7 @@
         fsd         fa5, FLOAT_ARG_OFFSET + 0x28(sp)
         fsd         fa6, FLOAT_ARG_OFFSET + 0x30(sp)
         fsd         fa7, FLOAT_ARG_OFFSET + 0x38(sp)
+#endif
 
         # Space for return block data (0x10 bytes)
 
@@ -113,6 +115,7 @@
 #ifdef TRASH_SAVED_ARGUMENT_REGISTERS
         PREPARE_EXTERNAL_VAR RhpFpTrashValues, a1
 
+#if __riscv_flen >= 64
         fld fa0, 0x00(a1)
         fld fa1, 0x08(a1)
         fld fa2, 0x10(a1)
@@ -121,6 +124,7 @@
         fld fa5, 0x28(a1)
         fld fa6, 0x30(a1)
         fld fa7, 0x38(a1)
+#endif
 
         PREPARE_EXTERNAL_VAR RhpIntegerTrashValues, a1
 
@@ -143,6 +147,7 @@ ALTERNATE_ENTRY ReturnFrom\FunctionName
         mv          t2, a0
 
         # Restore floating point registers
+#if __riscv_flen >= 64
         fld         fa0, FLOAT_ARG_OFFSET(sp)
         fld         fa1, FLOAT_ARG_OFFSET + 0x08(sp)
         fld         fa2, FLOAT_ARG_OFFSET + 0x10(sp)
@@ -151,6 +156,7 @@ ALTERNATE_ENTRY ReturnFrom\FunctionName
         fld         fa5, FLOAT_ARG_OFFSET + 0x28(sp)
         fld         fa6, FLOAT_ARG_OFFSET + 0x30(sp)
         fld         fa7, FLOAT_ARG_OFFSET + 0x38(sp)
+#endif
 
         # Restore the argument registers
         ld          a0, ARGUMENT_REGISTERS_OFFSET(sp)

src/coreclr/pal/inc/unixasmmacrosriscv64.inc

@@ -161,6 +161,9 @@ C_FUNC(\Name):
 
 // Reserve 64 bytes of memory before calling  SAVE_FLOAT_ARGUMENT_REGISTERS
 .macro SAVE_FLOAT_ARGUMENT_REGISTERS reg, ofs
+    // No-op without an FPU; the caller reserves the slots either way, so frame
+    // offsets are unaffected. Same for the other FP sequences in this file.
+#if __riscv_flen >= 64
     fsd  fa0, (\ofs)(\reg)
     fsd  fa1, (\ofs + 8)(\reg)
     fsd  fa2, (\ofs + 16)(\reg)
@@ -169,6 +172,7 @@ C_FUNC(\Name):
     fsd  fa5, (\ofs + 40)(\reg)
     fsd  fa6, (\ofs + 48)(\reg)
     fsd  fa7, (\ofs + 56)(\reg)
+#endif
 .endm
 
 // Reserve 64 bytes of memory before calling  SAVE_FLOAT_CALLEESAVED_REGISTERS
@@ -199,6 +203,7 @@ C_FUNC(\Name):
 .endm
 
 .macro RESTORE_FLOAT_ARGUMENT_REGISTERS reg, ofs
+#if __riscv_flen >= 64
     fld  fa0, (\ofs)(\reg)
     fld  fa1, (\ofs + 8)(\reg)
     fld  fa2, (\ofs + 16)(\reg)
@@ -207,6 +212,7 @@ C_FUNC(\Name):
     fld  fa5, (\ofs + 40)(\reg)
     fld  fa6, (\ofs + 48)(\reg)
     fld  fa7, (\ofs + 56)(\reg)
+#endif
 .endm
 
 .macro RESTORE_FLOAT_CALLEESAVED_REGISTERS reg, ofs
@@ -310,6 +316,7 @@ C_FUNC(\Name):
 
     // Save callee-saved floating point registers if requested (fs0-fs11)
     .if (__PWTB_PushCalleeSavedFloatRegs == 1)
+#if __riscv_flen >= 64
         fsd     fs0, (__PWTB_FloatCalleeSavedRegisters)(sp)
         fsd     fs1, (__PWTB_FloatCalleeSavedRegisters + 8)(sp)
         fsd     fs2, (__PWTB_FloatCalleeSavedRegisters + 16)(sp)
@@ -322,6 +329,7 @@ C_FUNC(\Name):
         fsd     fs9, (__PWTB_FloatCalleeSavedRegisters + 72)(sp)
         fsd     fs10, (__PWTB_FloatCalleeSavedRegisters + 80)(sp)
         fsd     fs11, (__PWTB_FloatCalleeSavedRegisters + 88)(sp)
+#endif
     .endif
 
 .endm
@@ -405,6 +413,7 @@ C_FUNC(\Name):
 
     // Save FP callee-saved registers (fs0-fs11 = f8,f9,f18-f27) at offset 0
     // RISC-V FP callee-saved: fs0=f8, fs1=f9, fs2-fs11=f18-f27
+#if __riscv_flen >= 64
     fsd   fs0,  0(sp)   // f8
     fsd   fs1,  8(sp)   // f9
     fsd   fs2,  16(sp)  // f18
@@ -417,6 +426,7 @@ C_FUNC(\Name):
     fsd   fs9,  72(sp)  // f25
     fsd   fs10, 80(sp)  // f26
     fsd   fs11, 88(sp)  // f27
+#endif
 
     // Set target to TransitionBlock pointer
     addi  \target, sp, 160

src/coreclr/pal/src/arch/riscv64/context2.S

@@ -26,6 +26,7 @@ LEAF_ENTRY RtlRestoreContext, _TEXT
     //64-bits FPR.
     addi t0, t4, CONTEXT_FPU_OFFSET
 
+#if __riscv_flen >= 64
     fld  f0, (CONTEXT_F0)(t0)
     fld  f1, (CONTEXT_F1)(t0)
     fld  f2, (CONTEXT_F2)(t0)
@@ -58,9 +59,12 @@ LEAF_ENTRY RtlRestoreContext, _TEXT
     fld  f29, (CONTEXT_F29)(t0)
     fld  f30, (CONTEXT_F30)(t0)
     fld  f31, (CONTEXT_F31)(t0)
+#endif
 
     lw t1, (CONTEXT_FLOAT_CONTROL_OFFSET)(t0)
+#if __riscv_flen != 0
     fscsr x0, t1
+#endif
 
 LOCAL_LABEL(No_Restore_CONTEXT_FLOATING_POINT):
 
@@ -205,6 +209,7 @@ LOCAL_LABEL(Done_CONTEXT_INTEGER):
 
     addi  a0, a0, CONTEXT_FPU_OFFSET
 
+#if __riscv_flen >= 64
     fsd  f0, (CONTEXT_F0)(a0)
     fsd  f1, (CONTEXT_F1)(a0)
     fsd  f2, (CONTEXT_F2)(a0)
@@ -237,8 +242,11 @@ LOCAL_LABEL(Done_CONTEXT_INTEGER):
     fsd  f29, (CONTEXT_F29)(a0)
     fsd  f30, (CONTEXT_F30)(a0)
     fsd  f31, (CONTEXT_F31)(a0)
+#endif
 
+#if __riscv_flen != 0
     frcsr t0
+#endif
     sd  t0, (CONTEXT_FLOAT_CONTROL_OFFSET)(a0)
 
 LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):