[NativeAOT] Fast interface dispatch helper for riscv64

[maximmenshikov]

Interface dispatch moved to a helper with a global dispatch cache in #123252. amd64 and arm64 got optimized helpers that check the monomorphic cell inline and probe the cache in assembly; riscv64 was left with the slow path, so every interface call goes through RhpUniversalTransition and the managed resolver.

Port the arm64 INTERFACE_DISPATCH macro: monomorphic cell check, then a GenericCache<Key, nint> probe using the same hash, the same quadratic reprobe and the same seqlock version check, falling back to RhpCidResolve and RhpCidResolve_Worker. Only temporaries are used, so nothing has to be spilled around the probe.

Three things differ from arm64, all forced by the ISA:

• arm64 gets its acquire loads from ldar and orders the value read against the version re-read with dmb ishld. RVWMO does not order a plain ld against later loads, so each of those becomes a fence r, r after the load.
• at the key compare only one temporary is still free, so the probe count travels in the upper bits of the index register instead of having a register of its own.
• the tail call to RhpUniversalTransitionTailCall is written out by hand: the tail pseudo-instruction expands through t1, which is carrying the thunk parameter.

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🔵 Needs a closer look

The hand-written concurrent assembly requires RISC-V hardware validation of ABI and memory-ordering behavior.

Pull request overview

Adds optimized NativeAOT interface dispatch for RISC-V 64, matching existing ARM64 cache behavior.

Changes:

• Adds monomorphic dispatch-cell checks.
• Probes the global dispatch cache with RISC-V memory ordering.
• Preserves slow-path resolution for cache misses.

File summaries

File	Description
src/coreclr/nativeaot/Runtime/riscv64/DispatchResolve.S	Implements cached RISC-V 64 interface dispatch.

Review details

• Files reviewed: 1/1 changed files
• Comments generated: 0
• Review effort level: Balanced

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