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JIT: Fix AVX state tracking for unrolled block operations #134410

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Merged
EgorBo merged 4 commits into from
Sep 22, 2026
Merged

JIT: Fix AVX state tracking for unrolled block operations #134410

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90b65c2
JIT: Fix AVX state tracking for unrolled block operations
EgorBo Sep 22, 2026
6640ca8
JIT: Centralize narrow SIMD zeroing in genSetRegToConst
EgorBo Sep 22, 2026
77e533a
JIT: Explain 128-bit zeroing of ZMM registers
EgorBo Sep 22, 2026
fc8c194
JIT: Unify SIMD zeroing comments
EgorBo Sep 22, 2026
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12 changes: 4 additions & 8 deletions src/coreclr/jit/codegenxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -381,7 +381,8 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, simd_t
}
else if (val32.IsZero())
{
emit->emitIns_SIMD_R_R_R(INS_xorps, attr, targetReg, targetReg, targetReg, INS_OPTS_NONE);
// VEX/EVEX 128-bit zeroing also clears the upper bits without dirtying upper vector state.
emit->emitIns_SIMD_R_R_R(INS_xorps, EA_16BYTE, targetReg, targetReg, targetReg, INS_OPTS_NONE);
}
else
{
Expand All @@ -400,13 +401,8 @@ void CodeGen::genSetRegToConst(regNumber targetReg, var_types targetType, simd_t
}
else if (val64.IsZero())
{
// Use VEX version because it's smaller (for zmm0-zmm15) than EVEX to zero a zmm register and still
// zeros the entire register:
//
// xorps zmm0, zmm0, zmm0 (6 bytes)
// xorps ymm0, ymm0, ymm0 (4 bytes)
//
emit->emitIns_SIMD_R_R_R(INS_xorps, EA_32BYTE, targetReg, targetReg, targetReg, INS_OPTS_NONE);
// VEX/EVEX 128-bit zeroing also clears the upper bits without dirtying upper vector state.
emit->emitIns_SIMD_R_R_R(INS_xorps, EA_16BYTE, targetReg, targetReg, targetReg, INS_OPTS_NONE);
}
else
{
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6 changes: 4 additions & 2 deletions src/coreclr/jit/lsraxarch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1459,7 +1459,9 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
if (willUseSimdMov)
{
buildInternalFloatRegisterDefForNode(blkNode, internalFloatRegCandidates());
SetContainsAVXFlags();
// Zero initialization uses a 128-bit xor, which also clears the upper vector bits.
SetContainsAVXFlags(src->IsIntegralConst(0) ? XMM_REGSIZE_BYTES
: m_compiler->roundDownSIMDSize(size));
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}

#ifdef TARGET_X86
Expand Down Expand Up @@ -1564,7 +1566,7 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
// no more than MaxInternalCount. Currently, it's controlled by getUnrollThreshold(memmove)
buildInternalFloatRegisterDefForNode(blkNode, internalFloatRegCandidates());
}
SetContainsAVXFlags();
SetContainsAVXFlags(simdSize);
}
else if (isPow2(size))
{
Expand Down
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