falcon

Linux capable RISC-V SoC with NVDLA for edge AI inference. The SoC is built on the Cheshire platform around a 64-bit CVA6 core (RV64IMAFDC, SV39 MMU) and integrates the nv_small configuration of NVDLA. It runs on a Xilinx VCU108 board, which has no hard ARM processing system, so the CVA6 does everything by itself: DRAM access through the MIG DDR4 IP, booting Linux and driving the NVDLA through the OpenDLA kernel module.

Citation

You can cite the paper (accepted but not published yet) as:

@inproceedings{celik2026falcon,
  title={FALCON: A Linux-Capable RISC-V SoC with NVDLA for Edge AI Inference},
  author={Celik, Seyyid Hikmet and Bolat, Alperen and Grosse Hokamp, Peer and Hui, Henry and Sezer, Sakir and Ergin, Oguz},
  booktitle={2026 IEEE 39th International System-on-Chip Conference (SOCC)},
  year={2026},
  organization={IEEE},
  note={to be published}
}

The NVDLA configuration bus (CSB) is connected to the Cheshire regbus and mapped at 0x40000000, the NVDLA data backbone (DBB) is an AXI-4 master on the crossbar and its interrupt is a PLIC source. From the Cheshire peripherals only UART, PLIC and CLINT are enabled. SoC and NVDLA share a single 50 MHz clock domain.

For my other tryings, some missing parts here, simulations, development process you can check these other repos:

https://github.com/celuk/cheshire-env

https://github.com/celuk/cheshire-env-nvdla

https://github.com/celuk/cheshire-env-nvdla-g2

https://github.com/celuk/cheshire-linux

https://github.com/celuk/cheshire-linux-nvdla

Environment Setup

Clone the repo and update the submodules:

git clone https://github.com/gdrlab/falcon

cd falcon

git submodule update --init --recursive

The tools for simulation and compilation come from a nix environment in cheshire-env-nvdla. If you do not have nix, check the Environment Setup part of secure-soc for installing it, then:

cd cheshire-env-nvdla && nix develop

For the FPGA flow you also need Vivado 2022.2 (set XILINX_VIVADO in Makefile) and Bender.

Running on a FPGA

Cheshire did not support VCU108, so I ported it and added the VCU108 support to Cheshire in this PR that you can check:

pulp-platform/cheshire#264

Build the VCU108 bitstream (Xilinx IPs are generated first, so it takes a while):

make chs-xilinx-vcu108

Program generated bitstream to the board:

make program <bitstream>

For other Cheshire targets and the general flow you may check the Cheshire docs.

Linux Boot

Linux, OpenSBI, BusyBox and the NVDLA software stack (KMD and UMD) ported for this SoC is here:

https://github.com/gdrlab/falcon-linux

U-Boot is not used. The boot payload is written into DRAM over UART (or JTAG) and then the modified zero stage bootloader in the bootrom jumps to OpenSBI, which boots the kernel with an embedded BusyBox initramfs. opendla.ko is loaded automatically at init.

Image	DRAM address
OpenSBI (fw_dynamic)	0x80000000
Device tree	0x80140000
Linux kernel (Image)	0x80200000

The whole flow (program bitstream, send dtb, kernel and OpenSBI over UART at 921600 baud) is to run linux on pure soft core running on FPGA:

make program_linux <ttyUSB number>

Then open the console (115200 baud):

make pico <ttyUSB number>

and run the models from the bash shell in linux console over UART with nvdla_runtime and .nvdla loadables generated by nvdla_compiler e.g.:

Starting shell...
~ # nvdla_runtime --image 0_8.jpg --loadable fast-math.nvdla
creating new runtime context...

To load same program from JTAG instead of UART you can check load_fw.gdb. For JTAG you don't need additional hardware since we are using internal USB JTAG of FPGA. In one terminal run make jtag and in another run make gdb and enter the commands in load_fw.gdb script or directly source it in the gdb terminal, after done you can see same shell in the third terminal you did e.g. make pico 1.

Note: Some paths in Makefile and other related files are left as absolute local paths, so fix them for your machine before running them.

Code References

In addition to submodules and bender dependencies, some codes were used from these repos directly or after some modification:

https://github.com/pulp-platform/cheshire

https://github.com/nvdla/hw

https://github.com/nvdla/sw

https://github.com/sifive/block-nvdla-sifive

https://github.com/LeiWang1999/ZYNQ-NVDLA