This repository holds the VHDL codes and Verilog codes of the course named VLSI. The following are the visualization of some codes.
Figure 1. Multiplexer VHDL visualization
Figure 2. Finite state machine states visualization
Figure 3. Up-down counter with D type Flip-flop VHDL visualization
Figure 4. Universal shift register Verilog visualization
Figure 5. RAM using only LEs by Verilog: