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V-L2-I1: lineage edges allow self-references; add CHECK source != target #42

Description

@hyperpolymath

Context

verisimdb_lineage_graph permits source_entity = target_entity and offers no cycle detection. The README's "DAG" claim is unenforced.

What to do

Add CHECK source_entity <> target_entity OR source_table <> target_table. (Cycle prevention is a runtime concern — track separately as V-L2-I2.)

Acceptance

  • CHECK constraint in generated DDL
  • DDL test asserts presence

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