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1. Constraint-Aware-Neural-Network-Systems Constraint-Aware-Neural-Network-Systems Public

   Exploring constraint-aware neural network design through LUT-based FPGA pruning and RadioML signal classification analysis.

   Python

2. Systolic-Array-Accelerator Systolic-Array-Accelerator Public

   4×4 systolic array accelerator in Verilog with cycle-level execution tracing and Python-based dataflow visualization

   Verilog 1

3. LUT-vs-MAC-Pipeline-RTL-Comparison LUT-vs-MAC-Pipeline-RTL-Comparison Public

   Verilog-based comparison of LUT vs MAC inference pipelines with event-driven latency measurement and cycle-accurate analysis

   Verilog

4. Hardware-Decision-Analytics-Tool Hardware-Decision-Analytics-Tool Public

   Constraint-first hardware design decision tool with feasibility filtering, Pareto analysis, and sensitivity-aware recommendations (Streamlit)

   Python