I am an Electrical & Computer Engineering student at Case Western Reserve University. My primary interest is in utilizing FPGAs in mixed-signal applications like SDRs and power management, as well as computer architecture and ultra low latency system design.
My repo is organized to show my best, completed projects, contributions to student orgs I am a part of, and collaborative homework repos. I will also tentatively showcase my PCB designs here.
DVB-S2 modulator for live video transmission targeting Xilinx on SDR.
RISC-V emulator and assembler.
This project emulates the RISC-V architecture in C. I confirmed operations with binaries from C programs as well as hand encoded instructions. Then, I also made a RISC-V Assembly assembler in OCaml that turned Assembly code into runnable binaries. I cross referenced it by running RISC-V Assembly programs into my custom Assembler, extracting the binaries, then running it into the emulator, and confirming the register outputs.
Through this project, I learned the RISC-V architecture and the functional programming paradigm via OCaml.
This project emulates a L2 Order Book Engine, keeping track of best spread across a stream of order instructions. I targeted a Cyclone V FPGA and ran tests via UART from my laptop. Essentially, the every time an instruction is sent, the order book will return the current best spread.
Through this project, I learned how order book engines work, how to use the Intel Altera FPGA ecosystem, and how to design critical RTL modules such as UART transceivers and CDC synchronizers. Additionally, I gained more familiarity with the C++ programming language.
Comfortable with: Python, C, Rust, MATLAB, SystemVerilog/Verilog
Pretty good at: C++, Java, Assembly, VHDL
Want to learn more: OCaml, Zig