This repository contains demo projects for various Xilinx Series 7 development boards. They are intended to give you a quick and easy template to use as a basis for your own projects, and also to demonstrate the current capabilites of the toolchain.
The test matrix dashboard shows the pass/fail status of every demo project across recent CI runs; the table below is the same matrix, embedded and updated by CI.
| project | heavy #64 | heavy #63 | smoke #98 | smoke #97 | heavy #62 | heavy #61 | heavy #60 | heavy #59 | pass rate |
|---|---|---|---|---|---|---|---|---|---|
blinky-digilent-arty |
· | · | ✔ | ✖ | · | · | · | · | 50% |
blinky-digilent-basys-3 |
· | · | ✔ | ✖ | · | · | · | · | 50% |
blinky-digilent-zybo |
· | · | ✔ | ✖ | · | · | · | · | 50% |
blinky-genesys2 |
· | · | ✔ | ✖ | · | · | · | · | 50% |
blinky-kc705 |
· | · | ✔ | ✖ | · | · | · | · | 50% |
blinky-qmtech |
· | · | ✔ | ✖ | · | · | · | · | 50% |
blinky-stlv7325 |
· | · | ✔ | ✖ | · | · | · | · | 50% |
ddr3-test-arty-s7 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
dsp-test-arty-s7 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-arty-s7 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-enclustra-kx2 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-hdmi-enclustra-kx2 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-hdmi-stlv7325 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-hpcstore-k420t |
✔ | ✔ | · | · | ✔ | ✔ | ✔ | ✔ | 100% |
litex-ddr-kc705 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-qmtech-artix7 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-qmtech-kintex7 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-ddr-stlv7325 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-minimal-arty-s7 |
· | · | ✔ | ✔ | · | · | · | · | 100% |
litex-sata-alientek-davincipro |
· | · | ✔ | ✔ | · | · | · | · | 100% |
picosoc |
· | · | ✔ | ✔ | · | · | · | · | 100% |
✔ pass · ✖ fail · … running / cancelled · · not in run. Newest run left. Cells link to the workflow job.
The matrix above is hardware-free: it proves a bitstream builds, not that it behaves. Three demos ship a host-side console check to run against a real board. These are manual checks by design — CI has no board attached, so nothing here runs in a workflow; flash the design and run the script yourself.
dsp-test-arty-s7/verify.py— captures the UART (115200 8N1) and checksp == a*bon every snapshot line, which is the signature of nextpnr-xilinx#159's missing DSP tile-constant bits.lutram-test-arty-s7/verify.py— checks a 64 x 8 distributed RAM, which yosys infers as 8 xRAM64X1Sin 2 SLICEM sites (nextpnr-xilinx#195: those used to abort at packing). Four write/read passes (address-as-data, complement, and two mixed patterns) are re-derived host-side from the streamedp<a> a=<addr> d=<data> e=<on-chip error count>lines, so a packer that agrees with itself still fails. This demo cannot be built by the pinned toolchain until #195 is released, so it is not in the matrix yet.ddr3-test-arty-s7/verify.py— drives the controller's UART bridge (9600 8N1: write bytes'a'..'z', read them back with'A'..'Z') and checks the write/read-back pairs. A served read proves the controller reached DONE_CALIBRATE and that data survives the DDR3 round trip; the four debug LEDs only show the calibration state and cannot be scripted.