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Artery: MFS support for AT32F43X, hal test - #39

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rusefillc merged 4 commits into
rusefi:stable_20.3.x.rusefi_clean_historyfrom
dron0gus:artery-dev-backport
Nov 3, 2023
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rusefillc merged 4 commits into
rusefi:stable_20.3.x.rusefi_clean_historyfrom
dron0gus:artery-dev-backport

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@dron0gus dron0gus commented Nov 3, 2023

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dron0gus force-pushed the artery-dev-backport branch from 7a7eb9d to 421ff88 Compare November 3, 2023 08:30
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dron0gus marked this pull request as ready for review November 3, 2023 08:30
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dron0gus requested a review from rusefillc November 3, 2023 08:37
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rusefillc merged commit e9d08d0 into rusefi:stable_20.3.x.rusefi_clean_history Nov 3, 2023
dron0gus pushed a commit to dron0gus/ChibiOS that referenced this pull request Sep 4, 2026
…23 (backport to 21.11.6) (rusefi#39)

🤖 Sheriff-prepared backport, for human review/merge.

Backport to **stable-21.11.x** (21.11.6) of github PR rusefi#34, merged on
`main` as `31e09a9b`. **HAL-only** — 21.11.x has no XHAL port.

On Cortex-M0/M0+/M23 `SCB->SHPR` is a word array driven through the
CMSIS `_SHP_IDX()`/`_BIT_SHIFT()` macros, which expect the *negative*
system exception number. `nvicSetSystemHandlerPriority()` passed the
positive ChibiOS handler index (`HANDLER_SYSTICK = 11`, …), so the
priority write hit the wrong SHPR slot — SysTick kept its reset priority
(0, highest) and SVCall's was corrupted. Converted to the matching
exception number (`handler - 12`). Affects every baseline-core port
(RP2040, STM32C0/G0/L0, STM32WL, …).

**Gates (local):** `RT-STM32L053…` (Cortex-M0+) builds clean;
`stylecheck.py` clean on changed lines. Same fix as the HW-validated
main change; HW re-confirmation on a baseline target is welcome but the
code is identical to `main`.

Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
rusefillc pushed a commit that referenced this pull request Sep 21, 2026
…23 (backport to 21.11.6) (#39)

🤖 Sheriff-prepared backport, for human review/merge.

Backport to **stable-21.11.x** (21.11.6) of github PR #34, merged on
`main` as `31e09a9b`. **HAL-only** — 21.11.x has no XHAL port.

On Cortex-M0/M0+/M23 `SCB->SHPR` is a word array driven through the
CMSIS `_SHP_IDX()`/`_BIT_SHIFT()` macros, which expect the *negative*
system exception number. `nvicSetSystemHandlerPriority()` passed the
positive ChibiOS handler index (`HANDLER_SYSTICK = 11`, …), so the
priority write hit the wrong SHPR slot — SysTick kept its reset priority
(0, highest) and SVCall's was corrupted. Converted to the matching
exception number (`handler - 12`). Affects every baseline-core port
(RP2040, STM32C0/G0/L0, STM32WL, …).

**Gates (local):** `RT-STM32L053…` (Cortex-M0+) builds clean;
`stylecheck.py` clean on changed lines. Same fix as the HW-validated
main change; HW re-confirmation on a baseline target is welcome but the
code is identical to `main`.

Co-authored-by: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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2 participants