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Hardware Metrics API

Status Stack Python

Ingest PPA FPGA

FastAPI + PostgreSQL service that ingests Vivado and OpenLane PPA metrics into one queryable store — no more copying WNS and LUT% out of Project Summary by hand.

Every RTL iteration on the Nexys A7 was generating the numbers in the screenshots below. The design journal is where the story lives; start with Automating Vivado + OpenLane PPA Extraction. This README is the map.

ALU Vivado Project Summary — timing, utilization, power ALU implemented design — floorplan and timing closure

Left: Vivado Project Summary for alu (WNS 7.449 ns · 0.128 W · LUT/FF 1%) · Right: implemented design on xc7a100tcsg324-1

metrics ingest parses reports like these into PostgreSQL. OpenLane metrics.json lands on the same runs table. Details and more screenshots: vivado-projects/README.md.


Why

Sanity is the fourth metric. Manual PPA scraping kills hardware momentum — see the origin log for the full Nexys A7 / Tomato / OpenLane context.

When friction appears, write a tool. Same pattern as Mango Tools and QueuePaste. Point the CLI at a Vivado project directory; discovery finds *.runs/ reports, parsers extract utilization / timing / power, upsert writes one row per (project, stage, run_tag).


Quickstart

docker compose up postgres -d
cp .env.example .env
pip install -e ".[dev]"
alembic upgrade head

metrics ingest vivado-projects/alu    # or: metrics ingest --all
uvicorn app.main:app --reload         # http://localhost:8000/docs

Full stack: docker compose up --build


What it does

Vivado *.runs/  ──┐
reports/*.rpt   ──┼──► parsers ──► PostgreSQL ◄── GET /runs
OpenLane JSON   ──┘         ▲
                     CLI / POST /ingest/*
Endpoint Role
GET /health Liveness
POST /ingest/vivado Upload utilization / timing / power reports
POST /ingest/vivado/path?path=... Ingest from server directory (dev)
POST /ingest/openlane Upload metrics.json
GET /runs List runs — filter by project, tool, stage

CLI: metrics ingest <path> · metrics ingest --all · Tests: pytest


Repository

Path What
log/ Design journal — source of truth for why
app/ API, parsers, CLI, ingest service
vivado-projects/ Nexys A7 benchmark RTL + Vivado projects
media/ Vivado screenshots (project summary, floorplan)
tests/fixtures/ Report snippets for pytest

Benchmarks

Six small designs on Nexys A7-100T (xc7a100tcsg324-1) — alu, adder, counter, fifo, multiplier, mux.

Documented PPA snapshots (post-route, from Vivado GUI):

Project WNS Power LUT FF IO
alu 7.449 ns 0.128 W 1% 1% 20%
mux 7.321 ns 0.121 W 1% 1% 18%

Open <name>/<name>.xpr → synthesis + implementation → metrics ingest vivado-projects/<name>. Workflow and figures: vivado-projects/README.md.


Status

August 2026 — Vivado + OpenLane ingest, REST API, Docker, and six benchmark designs are working. Auth, dashboard UI, and CI hooks are not started yet.


Author

Tyrone Marhguy — Computer Engineering '28, University of Pennsylvania

Email tmarhguy@gmail.com · tmarhguy@engineering.upenn.edu
GitHub @tmarhguy · Tomato

University of Pennsylvania Class of 2028

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