A Python package to use FPGA development tools programmatically.

Install Intel FPGA 'Quartus Prime' software on remote servers

Simulation and implementation flow for hardware description languages

Simple QAR (Quartus Archive) unpacker

SImple Python Script to convert binary data to MIF (Quartus Memory Initialization File) format

Quartus pin and Cadence Allegro net-list merger

🖋 Typeset Quartus II schematics using TikZ (LaTeX)

🖋 Typeset Quartus II waveform files using TikZ (LaTeX)

DE0 FPGA Labs (Terasic DE0, Cyclone III EP3C16F484C6) — collection of practical projects: arbitrary waveform generator (stage 2-3), ultrasonic RF echo envelope extraction with 7 methods + 3-peak detection + Qt GUI (stage 4).

FPGA development board (DE1) targetted lm32 based systems design for Verilog

Virtual GUI for controlling the Altera DE2-115 board.

FPGA Verilog 50Hz 工频陷波器 (IIR) — 心电信号 ECG 必备模块, 实测抑制 39 dB. 支持 ModelSim/Quartus/Icarus, 含 Q2.14 定点实现 + 测试激励 + 波形对比

High-performance FPGA-based CORDIC accelerator integrated with an ARM processor.

Logimentor VHDL fixed point math library