Skip to content

Update DIA to latest #58

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
Austin Lamb (Austin-Lamb) merged 1 commit into from
Jul 13, 2026
Merged

Update DIA to latest #58

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
Binary file modified src/ExternalDependencies/DIA/Dia2Lib.dll
View file
Open in desktop
Binary file not shown.
141 changes: 140 additions & 1 deletion src/ExternalDependencies/DIA/cvconst.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,8 @@ typedef enum CV_call_e
CV_CALL_INLINE = 0x17, // Marker for routines always inlined and thus lacking a convention
CV_CALL_NEAR_VECTOR = 0x18, // near left to right push with regs, callee pops stack
CV_CALL_SWIFT = 0x19, // Swift calling convention
CV_CALL_RESERVED = 0x20 // first unused call enumeration
CV_CALL_PRESERVE_NONE = 0x20, // All registers caller saved
CV_CALL_RESERVED = 0x21 // first unused call enumeration

// Do NOT add any more machine specific conventions. This is to be used for
// calling conventions in the source only (e.g. __cdecl, __stdcall).
Expand Down Expand Up @@ -83,6 +84,8 @@ enum CV_SourceChksum_t
CHKSUM_TYPE_MD5,
CHKSUM_TYPE_SHA1,
CHKSUM_TYPE_SHA_256,
CHKSUM_TYPE_SHA_384,
CHKSUM_TYPE_SHA_512,
};

//
Expand Down Expand Up @@ -201,6 +204,17 @@ enum BasicType
btChar16 = 32, // char16_t
btChar32 = 33, // char32_t
btChar8 = 34, // char8_t
btVector = 35, // SVE and other scalable vector types
};

// enumeration for scalable vector register types

enum ScalableVectorType
{
SVE_NONE = 0, // Not a scalable vector type
SVE_Z = 1, // SVE Z (data) registers
SVE_P = 2, // SVE P (predicate) registers
// Reserved for future scalable vector types
};


Expand All @@ -217,6 +231,7 @@ typedef enum CV_modifier_e
CV_MOD_CONST = 0x0001,
CV_MOD_VOLATILE = 0x0002,
CV_MOD_UNALIGNED = 0x0003,
CV_MOD_ATOMIC = 0x0004, // C11 _Atomic

// 0x0200 - 0x03ff - HLSL modifiers.

Expand Down Expand Up @@ -321,6 +336,7 @@ typedef enum CV_CFL_LANG
CV_CFL_SWIFT = 0x13, // Swift
CV_CFL_ALIASOBJ = 0x14,
CV_CFL_RUST = 0x15, // Rust
CV_CFL_GO = 0x16, // Go
} CV_CFL_LANG;


Expand Down Expand Up @@ -1893,6 +1909,61 @@ typedef enum CV_HREG_e
CV_ARM64_Q30H = 380,
CV_ARM64_Q31H = 381,

// Scalable Vector Extension (SVE)

CV_ARM64_Z0 = 382,
CV_ARM64_Z1 = 383,
CV_ARM64_Z2 = 384,
CV_ARM64_Z3 = 385,
CV_ARM64_Z4 = 386,
CV_ARM64_Z5 = 387,
CV_ARM64_Z6 = 388,
CV_ARM64_Z7 = 389,
CV_ARM64_Z8 = 390,
CV_ARM64_Z9 = 391,
CV_ARM64_Z10 = 392,
CV_ARM64_Z11 = 393,
CV_ARM64_Z12 = 394,
CV_ARM64_Z13 = 395,
CV_ARM64_Z14 = 396,
CV_ARM64_Z15 = 397,
CV_ARM64_Z16 = 398,
CV_ARM64_Z17 = 399,
CV_ARM64_Z18 = 400,
CV_ARM64_Z19 = 401,
CV_ARM64_Z20 = 402,
CV_ARM64_Z21 = 403,
CV_ARM64_Z22 = 404,
CV_ARM64_Z23 = 405,
CV_ARM64_Z24 = 406,
CV_ARM64_Z25 = 407,
CV_ARM64_Z26 = 408,
CV_ARM64_Z27 = 409,
CV_ARM64_Z28 = 410,
CV_ARM64_Z29 = 411,
CV_ARM64_Z30 = 412,
CV_ARM64_Z31 = 413,

CV_ARM64_P0 = 414,
CV_ARM64_P1 = 415,
CV_ARM64_P2 = 416,
CV_ARM64_P3 = 417,
CV_ARM64_P4 = 418,
CV_ARM64_P5 = 419,
CV_ARM64_P6 = 420,
CV_ARM64_P7 = 421,
CV_ARM64_P8 = 422,
CV_ARM64_P9 = 423,
CV_ARM64_P10 = 424,
CV_ARM64_P11 = 425,
CV_ARM64_P12 = 426,
CV_ARM64_P13 = 427,
CV_ARM64_P14 = 428,
CV_ARM64_P15 = 429,

// SVE first-fault status register
CV_ARM64_FFR = 430,

//
// Register set for Intel IA64
//
Expand Down Expand Up @@ -4020,6 +4091,74 @@ typedef enum CV_HREG_e
CV_AMD64_TMM7 = 854,
CV_AMD64_TILECFG = 855, // AMX tile cfg register

CV_AMD64_R16 = 856, // APX EGPRs
CV_AMD64_R17 = 857,
CV_AMD64_R18 = 858,
CV_AMD64_R19 = 859,
CV_AMD64_R20 = 860,
CV_AMD64_R21 = 861,
CV_AMD64_R22 = 862,
CV_AMD64_R23 = 863,
CV_AMD64_R24 = 864,
CV_AMD64_R25 = 865,
CV_AMD64_R26 = 866,
CV_AMD64_R27 = 867,
CV_AMD64_R28 = 868,
CV_AMD64_R29 = 869,
CV_AMD64_R30 = 870,
CV_AMD64_R31 = 871,

CV_AMD64_R16B = 872,
CV_AMD64_R17B = 873,
CV_AMD64_R18B = 874,
CV_AMD64_R19B = 875,
CV_AMD64_R20B = 876,
CV_AMD64_R21B = 877,
CV_AMD64_R22B = 878,
CV_AMD64_R23B = 879,
CV_AMD64_R24B = 880,
CV_AMD64_R25B = 881,
CV_AMD64_R26B = 882,
CV_AMD64_R27B = 883,
CV_AMD64_R28B = 884,
CV_AMD64_R29B = 885,
CV_AMD64_R30B = 886,
CV_AMD64_R31B = 887,

CV_AMD64_R16W = 888,
CV_AMD64_R17W = 889,
CV_AMD64_R18W = 890,
CV_AMD64_R19W = 891,
CV_AMD64_R20W = 892,
CV_AMD64_R21W = 893,
CV_AMD64_R22W = 894,
CV_AMD64_R23W = 895,
CV_AMD64_R24W = 896,
CV_AMD64_R25W = 897,
CV_AMD64_R26W = 898,
CV_AMD64_R27W = 899,
CV_AMD64_R28W = 900,
CV_AMD64_R29W = 901,
CV_AMD64_R30W = 902,
CV_AMD64_R31W = 903,

CV_AMD64_R16D = 904,
CV_AMD64_R17D = 905,
CV_AMD64_R18D = 906,
CV_AMD64_R19D = 907,
CV_AMD64_R20D = 908,
CV_AMD64_R21D = 909,
CV_AMD64_R22D = 910,
CV_AMD64_R23D = 911,
CV_AMD64_R24D = 912,
CV_AMD64_R25D = 913,
CV_AMD64_R26D = 914,
CV_AMD64_R27D = 915,
CV_AMD64_R28D = 916,
CV_AMD64_R29D = 917,
CV_AMD64_R30D = 918,
CV_AMD64_R31D = 919,

// Note: Next set of platform registers need to go into a new enum...
// this one is above 44K now.

Expand Down
Loading