fix(async,bus): harden generation and completion handling

[gly11]

Summary

This PR contains a small set of async/bus correctness fixes.

• preserve the full 16-bit bus generation in async transaction context and bus-reset lifecycle paths
• normalize OHCI ACK semantics from event codes before completing async transactions
• handle OUTPUT_MORE precursor descriptors when hardware reports completion on the following OUTPUT_LAST descriptor
• re-assert cycleMaster after cycleTooLong / bus reset and add explicit short/long bus reset support

Why

These changes make async transaction matching and bus-reset recovery more robust across bus-reset cycles and controller-specific OHCI completion behavior.

The bus-reset changes follow OHCI / IEEE 1394 behavior and align with the Linux firewire-ohci handling of cycle-too-long recovery, where cycleMaster is re-asserted after hardware clears it. The async completion changes make descriptor scanning and ACK interpretation more tolerant of controller-specific OHCI reporting.

They also make the core async/bus layer a safer foundation for future protocol work that depends on generation-correct response matching, split-transaction ACK handling, and reliable bus-reset recovery.

This supersedes #8 by folding the 16-bit generation fix into the broader async/bus correctness pass.

Test Plan

• ./build.sh --no-bump
• ctest --test-dir build/tests_build -R 'CompletionRefactorPlan|AsyncBusContract|AsyncSubsystemAccessor' --output-on-failure
• ctest --test-dir build/tests_build -R 'BusResetCoordinator|BusManagerGapOptimization' --output-on-failure

Results:

• build succeeded
• async-focused host tests passed: 20/20
• bus-focused host tests passed: 23/23

[mrmidi]

This PR covers clauses:

IEEE 1394-2008:

• Clause 8.3.2.2.1 (STATE_CLEAR register) and Clause 8.4.2.6 (Determination of the cycle master): Covers the requirement that an active cycle master must clear the cmstr bit upon detecting a CYCLE_TOO_LONG event, and the Bus Manager or IRM must subsequently re-assert it to restore operations.
• Clause 6.2.5.3 (Transaction label) and Clause 8.3.2.5 (TOPOLOGY_MAP registers): Enforces the rule that all nodes must discard queued asynchronous requests during bus resets to safely reuse transaction labels, and utilizes the 32-bit generation_number to prevent matching outdated cross-reset responses.
• Table 8-1 (Reset types) and Annex Q.9.2.1 (Arbitrated bus reset): Covers the timing and implementation differences between a standard long bus reset (~166.6 µs) and an arbitrated short bus reset (~1.3 µs) to minimize the disruption of isochronous traffic.
• Clause 6.2.6.2.2 (Acknowledge code) and Clause 7.3.5 (Dual-phase retry): Defines the normalization of ACK semantics (such as ack_complete, ack_data_error, ack_busy_X) and how they must map to transaction layer completion events and retry protocols.

OHCI 1.1 (May not be valid with OHC 1.2!)

• Handling OUTPUT_MORE and OUTPUT_LAST descriptor completion: Covered by Clause 7.1.5.2 (Command.xferStatus) and Clause 7.2.2.1 (Writing status back to context command descriptors). The specification explicitly states that upon the transmission completion of a packet, the hardware writes the status and timestamp only to the OUTPUT_LAST (or OUTPUT_LAST-Immediate) descriptor's xferStatus field. This validates the PR's fix to handle precursor OUTPUT_MORE descriptors correctly based on the completion reported by the following OUTPUT_LAST descriptor.

• Normalizing OHCI ACK semantics: Covered by Table 3-2 (Packet event codes). The specification defines how standard IEEE 1394 ACK codes (like ack_complete or ack_busy_X) are mixed with internal OHCI-generated event codes (like evt_flushed, evt_timeout, or evt_missing_ack) within the 5-bit event code field. This validates the PR's need to normalize these hardware-specific event codes back into standard transaction layer semantics before completing async transactions.

• cycleMaster clearing and re-assertion: Covered by Table 6-1 (IntEvent register description). Under the cycleTooLong bit definition, the OHCI specification mandates that the hardware itself shall clear the LinkControl.cycleMaster bit when an isochronous cycle lasts longer than the allotted time. This entirely validates the driver's software routine to step in and explicitly re-assert cycleMaster after cycle-too-long or bus reset events to restore the bus manager state.

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this comment intention is to preserve references to exact specifications

[mrmidi]

Thanks for contributing, @gly11
I'm always to see your PRs :)

[gly11]

Thanks, @mrmidi! That means a lot. Really appreciate your careful review and the spec notes. Always happy to help move ASFireWire forward :)